Safeguarding signal integrity with new and faster versions of DRAM.
As DRAM gets faster, timing constraints, jitter, and signal integrity become harder to control. The real challenge is to understand what can go wrong early in the design process, and that becomes more complex with each new version of memory and higher signal speeds. Stephen Slater, product manager for EDA products at Keysight, talks about how simulation can be applied to these issues, what to test for, and why new memories make it more difficult to achieve an optimal signal pattern.
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