Verifying A RISC-V Processor

What’s different from other RISC-V designs and what’s needed to ensure it works as planned.


Verifying an SoC is very different than verifying a processor due to the huge state space in the processor. In addition to the tools needed for an SoC, additional tools are required for a step and compare environment. Larry Lapides, vice president at Imperas, talks about the need to verify asynchronous events like interrupts, how to compare a reference model to RTL, and the need for both hardware/software co-design and architectural analysis.

Leave a Reply

(Note: This name will be displayed publicly)