tag: hardware/software co-design

Why Vision LLMs Force A Rethink Of Edge AI Hardware
By Athish Rao - 14 May, 2026 - Comments: 0

As vision-centric large language models move on-device, performance measured in raw TOPS is no longer enough. Architectures need to be built around real workloads, memory behavior, and sustained utilization, especially at the edge. Vision LLMs are changing the edge AI equation For the last decade, most edge AI silicon has been built to do one job extremely well: run convolutional networks for... » read more

Hardware From Specifications Using AI
By Brian Bailey - 06 May, 2026 - Comments: 0

There is a lot of excitement these days surrounding the idea that AI could make it possible to go from a specification to a design with absolutely no hardware skills. Well, get in line, because this is the umpteenth potential technology that was going to make that possible. Don't get me wrong, it just might do it, but will this be an implementation that is reliable, have decent performance, ... » read more

AI Power on the Edge
By Brian Bailey - 12 Mar, 2026 - Comments: 0

Key takeaways Power and thermal become primary design considerations, not just optimizations. Hardware architectures need to be developed from the ground up. Hardware/software/model co-development is essential. Implementing AI on the edge is driven by a different set of metrics than training or even inference in the cloud. It makes power a first-class citizen, if not the mos... » read more

Hardware Technologies And Algorithms for Vector Symbolic Architectures (Purdue Univ., Georgia Tech)
By Technical Paper Link - 26 Aug, 2025 - Comments: 0

A new technical paper titled "Cross-Layer Design of Vector-Symbolic Computing: Bridging Cognition and Brain-Inspired Hardware Acceleration" was published by researchers at Purdue University and Georgia Institute of Technology. Abstract "Vector Symbolic Architectures (VSAs) have been widely deployed in various cognitive applications due to their simple and efficient operations. The widesprea... » read more

Power Gating Enabling in NPUs (Univ. of Illinois Urbana-Champaign)
By Technical Paper Link - 15 Aug, 2025 - Comments: 0

A new technical paper titled "ReGate: Enabling Power Gating in Neural Processing Units" was published by researchers at the University of Illinois Urbana-Champaign. Abstract "The energy efficiency of neural processing units (NPU) is playing a critical role in developing sustainable data centers. Our study with different generations of NPU chips reveals that 30%–72% of their energy consump... » read more

HW/SW Co-Design Toolset for RISC-V (Tampere Univ.)
By Technical Paper Link - 21 Jul, 2025 - Comments: 0

A new technical paper titled "Automatically Retargeting Hardware and Code Generation for RISC-V Custom Instructions" was published by researchers at the Tampere University. Abstract "Custom instruction (CI) set extensions are beneficial for increasing performance and energy efficiency in a set of target applications. For rapid prototyping of these types of application-specific processors, d... » read more

Developing Workflows To Streamline System-Level Design
By Ann Mutschler - 28 Aug, 2024 - Comments: 0

Experts At The Table: One of the big challenges facing EDA companies is explaining to customers what's possible, how to streamline their designs, and what can be accomplished at what level of risk. Semiconductor Engineering sat down to talk about how relationships are fundamentally changing between EDA companies and their customers Michal Siwinski, chief marketing officer at Arteris; Chris Muet... » read more

Verifying A RISC-V Processor
By Ed Sperling - 17 Oct, 2023 - Comments: 0

Verifying an SoC is very different than verifying a processor due to the huge state space in the processor. In addition to the tools needed for an SoC, additional tools are required for a step and compare environment. Larry Lapides, vice president at Imperas, talks about the need to verify asynchronous events like interrupts, how to compare a reference model to RTL, and the need for both hardwa... » read more

Software-Hardware Co-Design Becomes Real
By Brian Bailey - 27 Sep, 2021 - Comments: 1

For the past 20 years, the industry has sought to deploy hardware/software co-design concepts. While it is making progress, software/hardware co-design appears to have a much brighter future. In order to understand the distinction between the two approaches, it is important to define some of the basics. Hardware/software co-design is essentially a bottom-up process, where hardware is deve... » read more

SoC Co-Emulation Using Zynq Boards
By Michelle Mata - 27 Feb, 2020 - Comments: 0

Have you ever worked on a group project where you had to combine your work with that of a colleague of a different engineering discipline but the absence of an efficient means of doing so affected the project’s overall outcome? Well, for software and hardware engineers developing an SoC, the merging of their respective engineering efforts for verification purposes is a big challenge. Early... » read more

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