SoC Co-Emulation Using Zynq Boards

Early and accurate hardware and software co-verification can eliminate several ARM-based SoC challenges.


Have you ever worked on a group project where you had to combine your work with that of a colleague of a different engineering discipline but the absence of an efficient means of doing so affected the project’s overall outcome? Well, for software and hardware engineers developing an SoC, the merging of their respective engineering efforts for verification purposes is a big challenge.

Early access to hardware-software co-verification allows hardware and software teams to work concurrently and set the foundation to a successful SoC project. However, many co-emulation methodologies are based on processor virtual models which are not accurate representations of the design. Fortunately, Aldec has a solution that integrates an ARM-based SoC from Xilinx, specifically a Zynq UltraScale+ MPSoC, with the largest Xilinx UltraScale FPGA. Since the Zynq device includes the hard IP of the ARM processor, our solution provides an accurate representation of the ARM-based SoC design for co-verification.

Figure 1: HW/SW Co-Verification

Design specification is the first step of the design flow in which the required specifications of the product are defined. By defining the features, requirements, and functionalities, we set the foundation for the design.

Next comes IP-based design and RTL coding, which consists of writing code for custom functional blocks in a hardware description language such as VHDL, Verilog or SystemVerilog. Along with the RTL code, testbenches are created to simulate and ensure functionality of the design according to its specifications. Riviera-PRO can be used to create testbenches and debug a design during simulation. Riviera-PRO is an advanced verification platform that provides high performance simulation and advanced debugging in VHDL, Verilog, SystemVerilog, SystemC, and mixed languages.

Software development starts in parallel with RTL coding. However, software and hardware developers seldom, if ever, communicate during this stage. The lack of communication between the two teams creates challenges such as not having an accurate hardware model for software development and debugging. Aldec’s solution enables early and accurate hardware and software co-verification using the ARM hardened core inside the TySOM-3-ZU7EV device, as shown in Figure 1, eliminating several ARM-based SoC verification challenges.

But what are the challenges?
Figure 2 shows the typical hardware and software components of SoCs. Challenges include not having access to the ARM pure RTL codes nor virtual platform, an accurate and fast hardware model for software development, low HDL simulation speed, and a limited number of tests with which to cover all the design functionality. As a design becomes larger and more complex, so simulation takes longer to run; sometimes up to a few months. Since it is not possible to develop a direct test to verify the whole functionality of an SoC design, we are faced with using a constrained random verification methodology, like UVM, to improve functional coverage. However, constrained random tests generate extremely long test sequences, which then becomes a bottleneck in the verification process. Moreover, the constrained random methodology doesn’t address the disconnected verification of hardware and software. The design would therefore benefit from co-emulation, which handles designs with a large number of gates without speed degradation; along with providing other benefits.

Figure 2: Hardware & Software Components of SoCs

What is co-emulation?
Co-emulation allows building a complete SoC design model for pre-silicon verification combining several techniques and their inherent assets into one robust platform. A co-emulation platform consists of an FPGA-based emulator, like Aldec’s HES-DVM, emulating either the SoC hardware (at the system-level) or only some of its blocks (block-level) and simulating virtual models that will mimic real-world operating conditions and peripherals.

The great benefit of co-emulation is that you can model different sub-systems in various ways and combine them into one robust and complete SoC, which helps you to verify software and hardware together. Standard blocks – such as a CPU, GPU or a block of memory – can run in a virtual environment or as real hardware on a daughter-card connected to FPGA-based emulator.

The virtual platform or virtual peripherals run on a host workstation connected to the emulated design using SCE-MI transactors, where SCE-MI is an Accellera standard that allows the transfer of messages between virtual models and an emulator. In-circuit emulation (ICE), also used in co-emulation, is when real devices are connected to the emulator to verify the emulated design with the devices that will be part of the design or its operating environment. Software debuggers are necessary when an SoC requires software and firmware verification. To learn more detail about co-emulation environments, please click here.

Co-emulation HW Flow
The Aldec TySOM-3 board has a Zynq MPSoC. It includes an ARM Cortex-A53 quad core processing system and programmable FPGA logic. As for the Aldec HES boards, they offer large capacity FPGAs, such as the Xilinx UltraScale US440, for implementing larger design blocks for emulation. By combining the large reconfigurable FPGA logic of the HES with the ARM processor in the TySOM board, hardware and software components can be verified together.

Figure 3 shows a co-emulation platform created using a TySOM-3 with ARM Cortex board to a HES-US-440 FPGA-based board along with Aldec’s HES-DVM software.

Figure 3: Co-Emulation Hardware Setup

Additionally, the TySOM-3 board can be connected to many peripherals including HDMI, Ethernet, QSFP+, DDR4, and SATA. The FMC connector provides an extension capability, meaning we can connect the TySOM-3 board to a bigger FPGA board or to daughter cards.

The logical connection between TySOM and the emulated design part in the HES board is via the AXI bus. We reach the AXI bus through the FMC connector to integrate the TySOM-3 board’s CPU ARM Cortex subsystem to the rest of the SoC in the emulator as shown in Figure 4.

The physical connection is made with a HOST2HOST daughter card and the Aldec AXI bridge using GTX lines for reliable and high throughput data transfers. The HES-US-440 board provides the largest Xilinx Virtex UltraScale FPGA, and its resources are equivalent to about 26 million ASIC gates. Aldec also has other HES boards that can be used if a larger capacity is needed.

Figure 4: Co-Emulation Block Diagram

Co-emulation SW flow
Figure 3 and Figure 4 show the connection of the TySOM-3 board to the HES Emulator that allows us to implement the entire SoC design on this platform. Furthermore, the SoC and the host workstation can be connected through SCE-MI transactors if we need to develop a testbench, testing application or connect to virtual peripherals. The software debugger can then be used to control the ARM Cortex processor inside the TySOM-3 board through a standard JTAG port. At the same time, the hardware debugger that is part of HES-DVM, allows us to debug the hardware running on the HES-US-440 board. The hardware debugger tool provides a GUI where we can select debug probes. We can then use Riviera-PRO to view the waveform captured by the hardware debugger. Thus, Aldec’s emulation platform will provide the complete hardware and software co-verification environment for an ARM-based SoC.

This allows the software team to gain a better insight into the hardware operation and allows the hardware team to receive additional, and, more importantly, a real-world scenario ‘testbench’ in the form of software running on an ARM processor. Co-verification reduces the wait time for the prototype to begin software testing.

Thanks to co-verification allowing software and hardware components to be verified concurrently, we eliminate the need to wait for working silicon before software testing. Also, virtual peripherals that simulate a real-world environment provides better hardware verification, which provides a better understanding of the hardware model and allows the software team to communicate with the hardware team.

Introducing the ARM hardware model to co-verification provides a 100% accurate hardware platform with ARM Cortex-A53, Cortex-R5, and Mali-400 GPU, as well as providing an easy connection via AMBA AXI and various peripherals that are immediately available to the user, among other benefits.

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