tag: constrained random

The True Cost Of Software Changes
By Brian Bailey - 22 Jun, 2023 - Comments: 2

Safety and security are considered to be important in a growing number of markets and applications. Guidelines are put in place for the processes used to develop either the hardware or the software, but what they seem to ignore is that neither exists in a vacuum. They form a system when put together. Back when I was developing tools for hardware-software co-verification, there were fairly co... » read more

A New Year’s Wish
By Brian Bailey - 26 Jan, 2023 - Comments: 0

Every year I run a predictions article. It is a mashup of ideas from many people within the industry, and while many predictions are somewhat self-serving, there are other which come more from the heart — or perhaps they are dreams rather than expectations. I see hope in some of those, particularly the ones that look toward sustainability within our industry, and of our industry. Just like... » read more

ML And UVM Share Same Flaws
By Brian Bailey - 28 Jul, 2022 - Comments: 1

A number of people must be scratching their heads over what UVM and machine learning (ML) have in common, such that they can be described as having the same flaws. In both cases, it is a flaw of omission in some sense. Let's start with ML, and in particular, object recognition. A decade ago, Alexnet, coupled with GPUs, managed to beat all of the object detection systems that relied on tradit... » read more

Measuring The Complexity Of Processor Bugs To Improve Testbench Quality
By Philippe Luc - 28 Apr, 2022 - Comments: 0

I am often asked the question “When is the processor verification done?” or in other words “how do I measure the efficiency of my testbench and how can I be confident in the quality of the verification?” There is no easy answer. There are several common indicators used in the industry such as coverage and bug curve. While they are absolutely necessary, these are not enough to reach the ... » read more

Ethical Coverage
By Brian Bailey - 27 Jan, 2022 - Comments: 1

How many times have you heard statements such as, "The verification task quadruples when the design size doubles?" The implication is that every register bit that is created has doubled the state space of the design. It gives the impression that complete verification is hopeless, and because of that little progress has been made in coming up with real coverage metrics. When constrained rando... » read more

Intelligent Coverage Optimization: Verification Closure In Hyperdrive
By Anika Malhotra - 28 Oct, 2021 - Comments: 0

Coverage dominates every aspect of verification for today’s complex IP and chip designs. Coverage metrics provide critical feedback on what has been verified and what has not, especially when automated stimulus generation techniques are used. All modern hardware design and verification languages include constructs for functional coverage specification and support a range of structural coverag... » read more

Using AI And Bugs To Find Other Bugs
By Ann Mutschler - 24 Nov, 2020 - Comments: 0

Debug is starting to be rethought and retooled as chips become more complex and more tightly integrated into packages or other systems, particularly in safety- and mission-critical applications where life expectancy is significantly longer. Today, the predominant bug-finding approaches use the ubiquitous constrained random/coverage driven verification technology, or formal verification techn... » read more

Simplifying And Speeding Up Verification
By Ed Sperling - 16 Jun, 2020 - Comments: 1

Semiconductor Engineering sat down to discuss what's ahead for verification with Daniel Schostak, Arm fellow and verification architect; Ty Garibay, vice president of hardware engineering at Mythic; Balachandran Rajendran, CTO at Dell EMC; Saad Godil, director of applied deep learning research at Nvidia; Nasr Ullah, senior director of performance architecture at SiFive. What follows are excerpt... » read more

SoC Co-Emulation Using Zynq Boards
By Michelle Mata - 27 Feb, 2020 - Comments: 0

Have you ever worked on a group project where you had to combine your work with that of a colleague of a different engineering discipline but the absence of an efficient means of doing so affected the project’s overall outcome? Well, for software and hardware engineers developing an SoC, the merging of their respective engineering efforts for verification purposes is a big challenge. Early... » read more

Going Deep Or Broad With Formal?
By Ann Mutschler - 28 Mar, 2018 - Comments: 0

Whether to apply [getkc id="33" comment="formal verification"] technology to semiconductor design broadly or deeply is a tough question. It hinges on what is the best way to achieve maximum ROI. Do you want to identify hard to find bugs, and get a certain level of confidence about a block? Where should the effort be placed? Is it by going deep, meaning a team of specialists or experts must b... » read more

← Older posts

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2024 SMG   |  Terms of Service  |  Privacy Policy