tag: constrained random

Faster Verification Debug With AI
By Taruna Reddy - 28 May, 2026 - Comments: 0

Every stage of semiconductor development takes longer and requires more effort with each new generation of chips. At no stage is this more apparent than functional verification. Industry consensus is that verification consumes roughly two-thirds of development time and resources. Within verification, debug is the most challenging step, consuming a third to two-thirds of the effort. Any serious ... » read more

The Verification Conundrum
By Brian Bailey - 02 Feb, 2026 - Comments: 2

When constrained random test pattern generation became the de facto way to verify designs, reference models became necessary to check that a design was producing the correct output. These were often distributed across several models, such as checkers, scoreboards and assertions. Another model that had to be created was the coverage model. It was required because you had to know if a generate... » read more

Spray And Pray Wastes Power
By Brian Bailey - 24 Nov, 2025 - Comments: 0

For quite some time I have felt that the way the industry approaches power is less than optimal. Techniques such as clock gating and power gating have been used to reduce the amount of unnecessary activity and leakage, but is there more activity that does not contribute to an intended action? While unnecessary activity may be unimportant in the functional sense, it all represents power that ... » read more

Debugging SystemVerilog Constraint Randomization: A Comprehensive Guide
By Rich Chang - 25 Jul, 2024 - Comments: 0

SystemVerilog constraint randomization is a powerful methodology for generating realistic and diverse test scenarios in the realm of hardware design verification. However, like any complex methodology, it can sometimes be challenging to debug when an unexpected issue arises. In this article, we will explore common debug techniques and strategies to help you effectively troubleshoot your SystemV... » read more

The True Cost Of Software Changes
By Brian Bailey - 22 Jun, 2023 - Comments: 2

Safety and security are considered to be important in a growing number of markets and applications. Guidelines are put in place for the processes used to develop either the hardware or the software, but what they seem to ignore is that neither exists in a vacuum. They form a system when put together. Back when I was developing tools for hardware-software co-verification, there were fairly co... » read more

A New Year’s Wish
By Brian Bailey - 26 Jan, 2023 - Comments: 0

Every year I run a predictions article. It is a mashup of ideas from many people within the industry, and while many predictions are somewhat self-serving, there are other which come more from the heart — or perhaps they are dreams rather than expectations. I see hope in some of those, particularly the ones that look toward sustainability within our industry, and of our industry. Just like... » read more

ML And UVM Share Same Flaws
By Brian Bailey - 28 Jul, 2022 - Comments: 1

A number of people must be scratching their heads over what UVM and machine learning (ML) have in common, such that they can be described as having the same flaws. In both cases, it is a flaw of omission in some sense. Let's start with ML, and in particular, object recognition. A decade ago, Alexnet, coupled with GPUs, managed to beat all of the object detection systems that relied on tradit... » read more

Measuring The Complexity Of Processor Bugs To Improve Testbench Quality
By Philippe Luc - 28 Apr, 2022 - Comments: 0

I am often asked the question “When is the processor verification done?” or in other words “how do I measure the efficiency of my testbench and how can I be confident in the quality of the verification?” There is no easy answer. There are several common indicators used in the industry such as coverage and bug curve. While they are absolutely necessary, these are not enough to reach the ... » read more

Ethical Coverage
By Brian Bailey - 27 Jan, 2022 - Comments: 1

How many times have you heard statements such as, "The verification task quadruples when the design size doubles?" The implication is that every register bit that is created has doubled the state space of the design. It gives the impression that complete verification is hopeless, and because of that little progress has been made in coming up with real coverage metrics. When constrained rando... » read more

Intelligent Coverage Optimization: Verification Closure In Hyperdrive
By Anika Malhotra - 28 Oct, 2021 - Comments: 0

Coverage dominates every aspect of verification for today’s complex IP and chip designs. Coverage metrics provide critical feedback on what has been verified and what has not, especially when automated stimulus generation techniques are used. All modern hardware design and verification languages include constructs for functional coverage specification and support a range of structural coverag... » read more

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