Challenges In RISC-V Verification

How to debug a multi-core chip and ensure it will be cache coherent and secure.


Designing a single-core RISC-V processor is relatively easy, but verifying it and debugging it is a different story. And it all becomes more complicated when multiple cores are involved, and when those cores need to be cache-coherent. Ashish Darbari, CEO of Axiomise, talks with Semiconductor Engineering about using assertions and formal verification technology to find bugs and prove coherency is not broken and that there are no hidden Trojans or other security weaknesses in the design.

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