category: Top Stories

category: Auto, Security & Edge AI

Designing Chips That Can Explain Themselves
By Ann Mutschler - 17 Jun, 2026 - Comments: 1

Key Takeaways: On-die telemetry gives architects a path to replace worst-case design margin with measured silicon behavior, improving PPA without compromising resilience. As monitor density and control-loop speed increase, observability must be architected hierarchically across local hardware response, on-die processing, and fleet-level learning. The real payoff is architectural: str... » read more

Swapping Out Chiplets: I/Os Vs. Compute
By Liz Allan - 28 May, 2026 - Comments: 0

Key Takeaways: Companies can save time and money by swapping out a compute, memory, or I/O chiplet to gain technology improvements, while keeping the other dies stable. Chip architects may choose to keep their I/Os stable and swap out compute to move from a 5nm process node to 3nm to achieve performance and power improvements, or swap out memory from LPDDR5X to LPDDR6. Swapping out... » read more

Observability Is Essential For Modern Silicon
By Ann Mutschler - 28 May, 2026 - Comments: 0

Experts At The Table: In-silicon observability — also known as on-die or on-chip visibility — is becoming increasingly important for managing the performance, reliability, and security of today’s high-performance systems. Semiconductor Engineering sat down to discuss this with Andy Nightingale, vice president of product management and marketing at Arteris; Nandan Nayampally, chief commerc... » read more

Options Grow For Standardizing Data Movement And Sharing Resources
By Ed Sperling - 20 May, 2026 - Comments: 0

Semiconductor Engineering sat down to discuss memory interfaces, interconnects, and memory access scaling with Madhumita Sanyal, senior director of technical product management at Synopsys; Swadesh Choudhary, senior principal engineer at Intel; Siamak Tavallaei, senior principal engineer at Samsung SSI; and Mohsen Asad, senior director of technology at Credo. What follows are excerpts of a disc... » read more

Confusion Grows With More Interconnect Options And Tradeoffs
By Liz Allan - 18 May, 2026 - Comments: 0

Key Takeaways: Designers are frequently evaluating 5 or more different interconnects in a single system, each with a distinct purpose. While chip-to-chip (PCIe) and die-to-die (UCIe, BoW) technologies seem to be solving a similar problem, in practice they bring different challenges. PCIe, CXL, NVLink, and UALink are all active in the hyperscaler space, but Ethernet-based technologies... » read more

Using AI To Monitor Dashboards In Chips And Systems
By Ed Sperling - 06 May, 2026 - Comments: 0

Key Takeaways: New types of dashboards are being used in conjunction with AI to make sense of large quantities of data. These dashboards can be used to quickly identify and fix power and heat-related problems, such as hotspots or voltage droop. Future dashboards will likely be much more customizable for different users or applications. Chipmakers are starting to use AI to ma... » read more

Designing Chips In The Context Of Rapidly Evolving AI
By Ann Mutschler - 04 May, 2026 - Comments: 0

Key Takeaways: Agentic edge AI drives long-lived, tool-mediated loops with variable demands for compute, tokens, and memory. Edge PPA is dominated by memory hierarchy and data movement, forcing tight feature triage and robust RAS. Rapid model churn (multimodal, MoE, new formats) requires programmable, headroom-rich compute, interconnect, and runtime. Experts At The Table: Ch... » read more

Creating Agentic EDA Methodologies
By Brian Bailey - 30 Apr, 2026 - Comments: 1

Key takeaways Agentic methodologies need to be able to reason across multiple data formats and abstractions. It is not clear how much data from previous designs is useful in new designs. Standards may help, but the lack of them may only impact cost. The relationship between tools and methodologies is bidirectional. Tools enable methodologies, and methodologies are dependent ... » read more

NoC Coherency Challenges Balloon With AI SoCs And Chiplets
By Liz Allan - 30 Apr, 2026 - Comments: 0

Key Takeaways Data movement, congestion, and energy efficiency are key determiners of whether compute is usable. Different processors bring various coherency challenges. For example, a cache-coherent NoC for CPUs is expensive and harder to verify than an I/O-coherent NoC for an accelerator. Designers need to balance top-down performance with bottom-up physical engineering to effect... » read more

AI Growing Impact On Chip Design And EDA Tools
By Ed Sperling - 15 Apr, 2026 - Comments: 0

Key Takeaways Many workflows in the data center are customer-specific, which is part of the reason there is so much interest in agentic AI-enabled tools. Large systems companies are pressing EDA vendors for performance improvements to keep pace with their AI workflows. The makeup of design teams is changing as AI infiltrates more of the chip design process. Experts at the Ta... » read more

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