category: Intelligent System Design

category: Auto, Security & Edge AI

A Scalable Answer To Advanced-Node Characterization
By Rajshekharayya Hiremath - 28 May, 2026 - Comments: 0

If you're working on standard-cell libraries at 28 nm or below, you already know the math isn't in your favor. At the 130 nm node, a typical library had fewer than 100 cells and a handful of PVT corners. Fast-forward to 16/14 nm and beyond, libraries now contain 1,200+ cells across 200+ PVT corners. Every new SoC tape-out demands broader coverage for design robustness, and the characte... » read more

Unlocking High-Speed Serial Link Signal Integrity With AMI Model
By Priyadarshini N D - 30 Apr, 2026 - Comments: 0

As the demand for faster data rates in high-speed interfaces such as PCIe, USB, and DDR continues to escalate, maintaining signal integrity has become a significant challenge for engineers. Traditional SPICE-based simulations, while precise, often suffer from computational intensity, making it impractical to model the intricate behavior of high-speed signals across millions of bits. This is ... » read more

Shift Verification Left: AI Tools For Faster, Smarter Chip Design
By Hamid Shojaei - 26 Mar, 2026 - Comments: 0

Verification activities can consume up to 70% of an overall chip project's effort, underscoring the central challenge that verification poses in today's semiconductor development (Cadence SoC Verification report). The most time-consuming activities, debugging and coverage closure, require significant coordination between design and verification teams and largely dictate overall time-to-ma... » read more

Data Center Digital Twins: How Simulation Improves Design And Performance
By Veena Parthan - 26 Feb, 2026 - Comments: 0

Data center digital twins are transforming data center design from assumption-based planning to physics-backed simulation—well before the first rack is deployed. By combining physics simulations with real operational data, a data center digital twin enables teams to predict performance, reduce risk, and optimize capacity with measurable confidence. As power densities rise from AI and hype... » read more

Heterogeneous Multicore System IP
By Nayan Gaywala - 29 Jan, 2026 - Comments: 0

For many of today’s embedded applications, compute requirements demand multiple cores (compute units). These applications also run various types of workloads. A heterogeneous multicore system enables designers to reduce energy and area costs while meeting performance requirements across various workloads. Data crunching by these multiple cores also puts a huge demand on the interconnect and m... » read more

3D-IC Market Outlook: Technology Roadmaps, Readiness, And Design Implications
By Reela Samuel - 23 Dec, 2025 - Comments: 0

The 3D-IC market outlook is entering a decisive phase as the semiconductor industry transitions beyond the limits of traditional Moore's Law scaling. As performance, power efficiency, and system complexity outpace what planar integration can deliver economically, vertical integration and heterogeneous system design are no longer experimental; they are becoming foundational. Advanced packagin... » read more

What Is 3D-IC Technology? Fundamentals, Architecture, And Design Concepts
By Reela Samuel - 25 Nov, 2025 - Comments: 0

As process nodes continue to advance into the sub-micron era, the limitations of traditional scaling are becoming increasingly evident. Larger monolithic chips are facing challenges such as higher power density, routing congestion, and reduced yield. Three-dimensional integrated circuits (3D-IC) technology represents a breakthrough approach by stacking multiple dies vertically. This design red... » read more

Enhancing PCIe 6.0 Performance: Flit Sequence Numbers And Selective NAK Explained
By Felipe Gonçalves - 30 Oct, 2025 - Comments: 0

The Flit Sequence Number is a mechanism introduced in the PCIe 6.0 specification, accompanying the transition to Flit Mode operation. This enhancement supersedes the legacy transaction layer packet (TLP) sequence numbering, along with its associated acknowledgment and replay protocols. What is a Flit Sequence Number? Historically, each TLP carried an explicit sequence number, which, while con... » read more

Boosting AI Performance With CXL
By Vanessa Do - 25 Sep, 2025 - Comments: 0

As AI applications rapidly advance, AI models are being tasked with processing massive amounts of data containing billions – or even trillions – of parameters. Each large workload involves numerous iterations for data comparison, predictive calculations, and parameter results updating during training. Hence, there is a constant demand for flexible memory expansion and memory sharing among d... » read more

An Overview Of CXL Mode Alternate Protocol Negotiation
By Guo Yu - 28 Aug, 2025 - Comments: 0

The Peripheral Component Interconnect Express (PCIe) protocol has a very powerful feature called Alternate Protocol Negotiation (APN), which was introduced in the PCIe 5.0 specification. This feature allows the alternate protocols (non-PCIe) that use PCIe PHY layer to be enabled and provide their own implementation of the more abstract layers. One of the most common alternate protocols is th... » read more

← Older posts

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2026 SMG   |  Terms of Service  |  Privacy Policy