category: System-Level Design

category: Auto, Security & Edge AI

Designing Electro-Optical Chips
By Ann Mutschler - 23 Jul, 2026 - Comments: 0

Key Takeaways: Silicon photonics is moving into mainstream AI, data center, and communications systems, but the design flow still needs tighter integration between photonic, electronic, package, thermal, and system-level tools. Existing EDA infrastructure can be reused for photonics, but waveguides, optical phase, wavelength, polarization, thermal drift, and compact modeling require spe... » read more

Untangling Chip Traffic Jams
By Liz Allan - 23 Jul, 2026 - Comments: 0

Key Takeaways: Defining all possible cases of coherent and non-coherent traffic is non-trivial, and designers need to use a mix of hardware-assisted verification and simulation tools to do so. For NoCs connecting multiple dies, simulation is challenging due to the very large number of interconnects and multiphysics issues involving thermal and crosstalk. Advanced verification approac... » read more

Chip Policy: The UK Vs. The US Vs. EU Vs. India
By Nandan Nayampally - 23 Jul, 2026 - Comments: 0

As we’ve observed over our recent blogs, the semiconductor industry is reckoning internally with technological questions on densification, scale, overcoming the memory wall, making data movement more efficient and many other such challenges. But the power and impact of semiconductors has much higher visibility amongst global powers. Seeing how chips now feature in every diplomatic discussi... » read more

Realizing The Future Of 3D-IC: Final Scenario And Sign-off
By Keith Felton - 23 Jul, 2026 - Comments: 0

By Keith Felton and Todd Burkholder Multi-chiplet packages contain thousands of connections between chiplets, interposers, and package BGAs. After optimizing this complex connectivity, designers must identify related signal groups (interfaces or buses) and plan their path from the chiplet bump field to target bumps or BGA balls. This involves managing multiple groups, considering available r... » read more

Avoid The Hidden Bottleneck Of Integration At Scale
By Insaf Meliane - 23 Jul, 2026 - Comments: 0

Modern SoCs are no longer limited by how much compute they can integrate, but by how effectively that compute can be assembled into a consistent system. As AI-driven designs scale to hundreds or thousands of IP blocks that span internal, third-party, and reusable components, the act of connecting, configuring, and validating those elements has become the dominant engineering challenge. Integrat... » read more

From Future Vision To Running Hardware: Verification At DAC 2026
By Frank Schirrmeister - 23 Jul, 2026 - Comments: 0

At last year's DAC in San Francisco, I sat in "A Look into the Future of Verification," an Engineering Track special session debating where our discipline is headed — multi-language flows, AI co-pilots, portable stimulus, formal methods. The discussion was energizing, and what struck me then stayed with me since: whatever that future looks like, it has to execute somewhere. And increasingly, ... » read more

Why Chip Engineers Should Care About AI-Created Behavioral Models
By Sidharth Kannan - 23 Jul, 2026 - Comments: 0

You probably know this bottleneck too well: full transistor-level or physical simulations—whether analog circuit, electromagnetic, or thermal—can take weeks or even months. For complex designs, simulating every internal transistor in every block quickly becomes impractical. This is why creating accurate behavioral models is so important. A good behavioral model captures a block's input-o... » read more

The Impact Of AI Automation On Chip Design
By Brian Bailey - 23 Jul, 2026 - Comments: 0

Key Takeaways: Tools are currently built with a defined notion of how they will be used. For agentic solutions they will be transformed into collections of callable engines. Agents may be built by EDA companies for design houses or larger design houses may build their own, potentially transforming the EDA business model. The role of engineers will change, but exactly how is not certa... » read more

Enhancing System Observability
By Movellus - 23 Jul, 2026 - Comments: 0

Modern AI SoCs push power delivery networks to their physical limits, yet traditional monitoring leaves a visibility gap. This joint white paper from Siemens EDA and Movellus shows how hardware cross-triggering links Aeonic Insight voltage telemetry with Tessent Embedded Analytics functional monitoring for a single, time-aligned view of what happened and why. To read more, click here. » read more

The End Of Physics Silos In Engineering AI
By John Bruggeman - 23 Jul, 2026 - Comments: 0

Modern engineering software was built around an assumption that made sense for its time: different physics problems required different tools, solvers, and workflows. Structural analysis lived in one environment. Thermal modeling lived in another. Electromagnetics lived in a different stack. Over time, engineering workflows became fragmented into isolated software systems, disconnected solver... » read more

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