Blog Review: July 17


Mentor's John McMillan takes a look at the three general classes that have been established by IPC-2221B to reflect progressive increases in sophistication, functional performance requirements, and testing/inspection frequency for PCBs. Synopsys' Dinesh Siwal and Thenmozhy Kaliyamurthy point out the new features and improvements in DisplayPort 2.0, including greater speeds, better power effi... » read more

Breaking Down The Debug Process


Semiconductor Engineering sat down to discuss debugging complex SoCs with Randy Fish, vice president of strategic accounts and partnerships for UltraSoC; Larry Melling, product management director for Cadence; Mark Olen, senior product marketing manager for Mentor, a Siemens Business; and Dominik Strasser, vice president of engineering for OneSpin Solutions. Part one can be found here. What fol... » read more

Week In Review: Design, Low Power


Synopsys unveiled the latest version of its IC Compiler II place-and-route system, adding a common physical optimization infrastructure, new arc-based unified concurrent clock-and-data (CCD) optimization, physically-aware logic re-synthesis, and dynamic voltage drop-driven power shaping. Additionally, next-generation distributed parallelization, intelligent scenario management, efficient infras... » read more

System Bits: July 10


Light waves run on silicon-based chips Researchers at the University of Sydney’s Nano Institute and Singapore University of Technology and Design collaborated on manipulating light waves on silicon-based microchips to keep coherent data as it travels thousands of miles on fiber-optic cables. Such waves—whether a tsunami or a photonic packet of information—are known as solitons. The... » read more

Blog Review: July 10


Synopsys' Eric Huang takes a look at how backward compatibility with USB 2.0 is provided when the IO voltages of new nodes can't support 3.3V signaling and how eUSB2 can boost the signal and provide support for external or legacy peripherals. In a video, Mentor Colin Walls explains endianness in embedded systems with a look at what it is, when it matters, and how to accommodate it in code. ... » read more

EDA, IP Grow 16.3%


EDA and IP revenue rebounded in Q1, with all geographies reporting increases, according to the ESD Alliance Market Statistics Service. Total revenue increased to 16.3% to $2.606 billion, up from $2.241 billion in the same period in 2018. The global numbers do not reflect the impact of a trade war between the United States and China, which occurred in Q2, but they do point to a significant re... » read more

HW/SW Design At The Intelligent Edge


Adding intelligence to the edge is a lot more difficult than it might first appear, because it requires an understanding of what gets processed where based on assumptions about what the edge actually will look like over time. What exactly falls under the heading of Intelligent Edge varies from one person to the next, but all agree it goes well beyond yesterday’s simple sensor-based IoT dev... » read more

Week In Review: Design, Low Power


Si2's Unified Power Model has been approved as IEEE 2416-2019, a new Standard for Power Modeling to Enable System Level Analysis, which complements UPF/IEEE 1801-2018. UPM/IEEE 2416-2019 provides a set of power modeling semantics enabling system designers to model entire systems with flexibility. It supports power modeling from abstract design description to gate level implementation, providing... » read more

Blog Review: July 3


Cadence's Paul McLellan digs into 5G with a two-part post explaining the basics of the technology, what makes it so different from 4G, and the challenges ahead including the limitations of mmWave. Synopsys' Vikramjeet Bamel and Pankaj Sharma note the features that make GDDR6 a dominant memory in the high performance segment and allowing it to expand beyond graphics to automotive, AI, and AR/... » read more

System Bits: July 3


CMU prof gets a shot at new supercomputer The National Energy Research Scientific Computing Center will greet its Perlmutter supercomputing system in early 2020. The Cray-designed machine will be capable of 100 million billion floating operations per second. Zachary Ulissi of Carnegie Mellon University will be among the first researchers to use the supercomputer. "When this machine comes on... » read more

← Older posts