System Bits: May 21


Washable, wearable energy devices for clothing Researchers at the University of Cambridge collaborated with colleagues at China’s Jiangnan University to develop wearable electronic components that could be woven into fabrics for clothing, suitable for energy conversion, flexible circuits, health-care monitoring, and other applications. Graphene and other materials can be directly incorpor... » read more

Week In Review: Design, Low Power


Tools & IP Cadence introduced the Tensilica Vision Q7 DSP, which provides up to 1.82 TOPS and is specifically optimized for simultaneous localization and mapping (SLAM). The DSP has a very long instruction word (VLIW) SIMD architecture, an enhanced instruction set supporting 8/16/32-bit data types and optional VFPU support for single and half precision, and a number of iDMA enhancements in... » read more

Incremental System Verification


Semiconductor Engineering sat down to discuss the implications of having an executable specification that drives verification with Hagai Arbel, chief executive officer for VTool; Adnan Hamid, chief executive office for Breker Verification; Mark Olen, product marketing manager for Mentor, a Siemens Business; Jim Hogan, managing partner of Vista Ventures; Sharon Rosenberg, senior solutions archit... » read more

Blog Review: May 15


Cadence's Sean Dart shares an example of the kind of optimizations HLS tools can perform that would be difficult to find and implement by hand-coding RTL. Synopsys' Taylor Armerding takes a look at three cybersecurity initiatives from the U.S. government, from an IoT bill to improved voting machines, and whether they're likely to work. In a video, Mentor's Colin Walls points to why flashi... » read more

System Bits: May 14


Faster U.S. supercomputers on the way The U.S. Department of Energy awarded a contract for more than $600 million to Cray for an exascale supercomputer to be installed at the Oak Ridge National Laboratory during 2021. Cray will provide its Shasta architecture and Slingshot interconnect for what is dubbed the Frontier supercomputer. Advanced Micro Devices will have a key role in building the... » read more

Week In Review: Design, Low Power


Tools & IP Cadence uncorked the latest version of JasperGold formal verification platform, providing improvements to the proof-solver algorithm and orchestration by using machine learning to select and parameterize solvers to enable faster first-time proofs and optimize successive runs for regression testing. Additionally, it increases design compilation capacity by over 2x with 50% reduct... » read more

Blog Review: May 8


Synopsys' Taylor Armerding warns that the threat of cyber war on the financial system is a real possibility and points to four major vulnerability concerns. Cadence's Meera Collier takes a look at bees and technology, from smart hives to sensors that can be carried on the insects' backs. Mentor's Brent Klingforth argues that electrical and mechanic designers need to seamlessly share infor... » read more

System Bits: May 6


Transmitting data with a semiconductor laser Researchers at the Harvard John A. Paulson School of Engineering and Applied Sciences demonstrated a laser that can emit microwaves wirelessly, modulate them, and receive external radio frequency signals. “The research opens the door to new types of hybrid electronic-photonic devices and is the first step toward ultra-high-speed Wi-Fi,” said ... » read more

Week In Review: Design, Low Power


ANSYS acquired the assets of DfR Solutions, a developer of automated design reliability analysis software. Founded in 2004 and based in Maryland, DfR's tool translates ECAD and MCAE data into 3D finite element models, automates thermal derating and performs thermal and mechanical analysis of electronics earlier in the design cycle. "ANSYS brings industry-leading electronic simulation capabiliti... » read more

IP Requires System Context At 6/5/3nm


Driven by each successive generation of semiconductor manufacturing technology, complexity has reached dizzying levels. Every part of the design, verification and manufacturing is more complicated and intense the more transistors are able to be packed onto a die. For these reasons, the entire system must be taken into consideration as a whole – not just as individual building blocks as could ... » read more

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