category: System-Level Design

category: IoT, Security & Automotive

Blog Review: July 16
By Jesse Allen - 16 Jul, 2025 - Comments: 0

Synopsys' Bradley Geden and Manoz Palaparthi explain the difference between functional signoff and RTL signoff and why increased SoC complexity means that verification flows must now capture both the intent and the integrity of a design before it can move forward. Cadence's Frank Ferro finds that LPDDR isn't just for mobile devices anymore, with the new LPDDR6 standard bringing increased ban... » read more

AI In Chip Design: Tight Control Required
By Ed Sperling - 16 Jul, 2025 - Comments: 0

Executive Outlook: Semiconductor Engineering sat down with a panel of experts to talk about what's needed to effectively leverage AI, who benefits from it, and where software-defined hardware works best, with Bill Mullen, Ansys fellow; John Ferguson, senior director of product management at Siemens EDA; Chris Mueth, senior director of new markets and strategic initiatives at Keysight; Albert Ze... » read more

Silicon IP Revenue Spikes
By Ed Sperling - 15 Jul, 2025 - Comments: 0

EDA and silicon IP revenue grew 12.8% in Q1 2025, totaling $5.098 billion compared to $4.522 billion in the same period last year, but the real story was on the IP side, surging 29.6% year-over-year to $1.577 billion. Drilling deeper into those numbers, revenue for non-reporting IP companies — predominantly Arm — jumped 34.1% YoY to $1.031 billion. That was positive news for the IP marke... » read more

Startup Funding: Q2 2025
By Jesse Allen - 14 Jul, 2025 - Comments: 0

Investors were drawn to a wide range of innovative approaches in Q2 2025, backing startups developing superconducting logic, chips for an emerging number format, big data processors, and novel power semi architectures. At the same time, photonics continues to draw investment dollars due to its ability to move data faster and with less energy at both the chip-to-chip and data center levels. T... » read more

Blog Review: July 2
By Jesse Allen - 02 Jul, 2025 - Comments: 0

Synopsys’ Shankar Krishnamoorthy chats with industry experts about how the combination of AI and software-defined systems is driving a re-evaluation of engineering workflows and why chip, software, and system development must evolve in unison. Siemens’ Jake Wiltgen considers the rapidly evolving and growing challenge of performing DFT verification as designs scale, with complex hierarchi... » read more

Democratizing Design: How The CHIPS Act Is Reshaping EDA And Semiconductor Innovation
By Nilesh Kamdar - 02 Jul, 2025 - Comments: 1

After 26 years in the electronics industry, I've witnessed countless technological shifts, but few have been as transformative — or as promising — as what we're experiencing with the CHIPS Act. I spoke at a recent 62nd DAC panel discussion alongside industry colleagues Saverio Fazzari from Booz Allen Hamilton and Vivek Prasad from a non-profit organization established to operate the Nationa... » read more

Rethinking Chip Debug
By Priyank Jain - 30 Jun, 2025 - Comments: 0

By Priyank Jain and James Paris The semiconductor industry has spent decades mastering the art of integrated circuit physical verification. But as system-on-chip (SoC) designs push the boundaries of complexity—with more transistors, greater integration and larger silicon areas—the established debug strategies are breaking under the weight of scale. Today’s advanced chips can generate a... » read more

Iteration And Hallucination
By Brian Bailey - 26 Jun, 2025 - Comments: 0

Iteration loops have been a vital aspect of EDA flows for decades. Ever since gate delays and wire delays became comparable, it became necessary to find out if the result of a given logic synthesis run would yield acceptable timing. Over the years this problem became worse because one decision can affect many others. The ramifications of a decision may not have been obvious to an individual too... » read more

Mixed Messages Complicate Mixed-Signal
By Brian Bailey - 26 Jun, 2025 - Comments: 0

Several years ago, analog and mixed signal (AMS) content hit a wall. Its contribution to first-time chip failure doubled, and there is no evidence that anything has improved dramatically since then. Some see that the problem is likely to get worse due to issues associated with advanced nodes, while others see hope for improvement coming from AI or chiplets. Fig. 1: Cause of ASIC respins. S... » read more

Redefining SoC Design: The Shift To Secure Chiplet-Based Architectures
By Moshiko Emmer - 26 Jun, 2025 - Comments: 0

The semiconductor industry is undergoing a paradigm shift from monolithic system-on-chip (SoC) architectures to modular, chiplet-based designs. This transformation is driven by escalating design complexity, soaring fabrication costs, and the relentless pursuit of efficiency. However, as chiplet adoption accelerates, security becomes a critical concern, requiring robust measures to protect data,... » read more

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