Rethinking Competitive One Upmanship Among Foundries


The winner in the foundry business used to be determined by who got to the most advanced process node first. For the most part that benchmark no longer works. Unlike in the past, when all of the foundries and IDMs competed using basically the same process, each foundry has gone its own route. This is primarily due to the divergence of end markets, and the realization that as costs increase, ... » read more

EDA Forms The Basis For Designing Secure Systems


By Adam Cron and Brandon Wang As Internet of Things (IoT) devices rapidly increase in popularity and deployment, security risks are arising at all levels. It could be at the usability level such as social engineering, pretexting, phishing; at the primitive level such as cryptanalysis; at the software level such as client-side scripting, code injection; and now even at the hardware level. Dur... » read more

The Evolution Of Digital Twins


Digital twins are starting to make inroads earlier in the chip design flow, allowing design teams to develop more effective models. But they also are adding new challenges in maintaining those models throughout a chip's lifecycle. Until a couple of years ago, few people in the semiconductor industry had even heard the term "digital twin." Then, suddenly, it was everywhere, causing confusion ... » read more

Week In Review: Design, Low Power


Analog Devices (ADI) acquired the HDMI business of Invecas. “The acquisition of Invecas' HDMI business positions ADI to deliver more complete solutions throughout the entire customer journey – from chip, to certification, to end product," said John Hassett, Senior Vice President, Industrial and Consumer at Analog Devices. "We are thrilled to enhance ADI’s capabilities with the addition of... » read more

Engineering Within Constraints


One of the themes of DAC this year was the next phase of machine learning. It is as if CNNs and RNNs officially have migrated from the research community and all that is left now is optimization. The academics need something new. Quite correctly, they have identified power as the biggest problem associated with learning and inferencing today, and a large part of that problem is associated with ... » read more

Universal Verification Methodology Running Out Of Steam


For the past decade or so, the Universal Verification Methodology (UVM) has been the de facto verification methodology supported by the entire EDA industry. But as chips become more heterogeneous, more complex, and significantly larger, UVM is running out of steam. Consensus is building that some fundamental changes are required, moving tools up a level of abstraction and making them more ag... » read more

Open-Source Verification


Ask different people what open-source verification means and you will get a host of different answers. They range from the verification of open-source hardware, to providing an open-source verification infrastructure, to providing open-source stream generators or reference models, to open-source simulators and formal verification engines. Verification is about reducing risk. "Verification is... » read more

Computational Software: The Foundation Across Software Disciplines


You may have seen the term "computational software" more often recently. What are some prominent examples? Why do we in the electronic design automation (EDA) industry have to deal with math in the first place? Wasn't chip design all about drawing polygons at one point? I’m glad you asked! Computational software supports and manages the complexity of fundamental industry trends—hyperscal... » read more

RISC-V Gaining Traction


Part 1: Semiconductor Engineering sat down to discuss where and why RISC-V is doing well, with Zdenek Prikryl, CTO of Codasip; Helena Handschuh, a Rambus Security Technologies fellow; Louie De Luna, director of marketing at Aldec; Shubhodeep Roy Choudhury, CEO of Valtrix Systems; and Bipul Talukdar, North America director of applications engineering at SmartDV. What follows are excerpt of that ... » read more

Linting RISC-V Designs


As the open-source RISC-V instruction set architecture (ISA) continues to gain momentum, the growing number of RISC-V design solutions and their flexibility creates a problem when choosing the most reliable and robust solution from a number of contenders. Sure, a RISC-V IP design must be compliant to basic ISA standards and should contain a testing suite demonstrating that compliance. But sh... » read more

← Older posts