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category: System-Level Design

category: IoT, Security & Automotive

Week In Review: Design, Low Power
By Jesse Allen - 15 Oct, 2021 - Comments: 0

Nvidia acquired Oski Technology. Oski provides formal verification methodologies and consulting services, and Nvidia said that the acquisition will allow it to increase its investment in formal verification strategies. Oski's Gurugram, India, design center will become Nvidia's fourth engineering office in the country. Based in San Jose, Calif., it was founded in 2005. Terms of the deal were not... » read more

Using IP-XACT To Solve Design And Verification Problems
By Anika Malhotra - 13 Oct, 2021 - Comments: 0

As today’s SoC designs grow more complex and time-to-market (TTM) pressures rise, designers are looking for techniques to build and update designs easily. Key elements for addressing these SoC challenges include the incorporation of more commercial IP components, internal design IP reuse, and extensive automation of design and verification activities. Enhanced interoperability and reusability... » read more

Blog Review: Oct. 13
By Jesse Allen - 13 Oct, 2021 - Comments: 0

Cadence's Paul McLellan checks out what Google learned in developing multiple generations of its TPU processor, including unequal advancement of logic and memory, the importance of compiler of compatibility, and designing for total cost of ownership. Siemens EDA's Jake Wiltgen argues for the importance of linting as part of eliminating systematic failures in designs complying with ISO 26262.... » read more

Week In Review: Design, Low Power
By Jesse Allen - 08 Oct, 2021 - Comments: 0

Arteris IP plans to become a public company. It filed a registration statement with the SEC for an IPO, and intends to list on Nasdaq. The number of shares to be offered and the price range for the proposed offering have not yet been determined. Arteris IP provides network-on-chip interconnect IP, cache coherent interconnects, and packages to speed functional safety certification alongside IP d... » read more

Blog Review: Oct. 6
By Jesse Allen - 06 Oct, 2021 - Comments: 0

Arizona State University's Jae-sun Seo and Arm's Paul Whatmough introduce a fully-parallel and fully-pipelined FPGA accelerator for sparse CNNs that can eliminate off-chip memory access and also efficiently support elementwise pruning of CNN weights. Cadence's Paul McLellan highlights trends seen at the recent Hot Chips, from machine learning and advanced packaging driving higher performance... » read more

Week In Review: Design, Low Power
By Jesse Allen - 01 Oct, 2021 - Comments: 0

Valens Semiconductor began trading on the New York Stock Exchange as VLN after a merger with special-purpose acquisition company (SPAC) PTK Acquisition Corp. Valens offers high-speed connectivity chips for the audio-video and automotive markets, including its HDBaseT technology for connectivity between ultra-HD video sources and remote displays and its in-vehicle high-speed links. The transacti... » read more

Blog Review: Sept. 29
By Jesse Allen - 29 Sep, 2021 - Comments: 0

Cadence's Paul McLellan checks out two of the biggest chips presented at the recent Hot Chips: a graphics chip from Intel for an upcoming supercomputer and Cerebras' wafer-scale AI chip. Synopsys' Datsen Davies Tharakan lists the top five design challenges for electric vehicles and power semiconductors and why a robust design flow can accelerate the growth of hybrid and electric vehicles goi... » read more

EDA Vendors Widen Use Of AI
By Ed Sperling - 29 Sep, 2021 - Comments: 0

EDA vendors are widening the use of AI and machine learning to incorporate multiple tools, providing continuity and access to consistent data at multiple points in the semiconductor design flow. While gaps remain, early results from a number of EDA tools providers point to significant improvements in performance, power, and time to market. AI/ML has been deployed for some time in EDA. Still,... » read more

3D IC: Opportunities, Challenges, And Solutions
By Kenneth Larsen - 28 Sep, 2021 - Comments: 0

Nearly every big city reaches a point in its evolution when it runs out of open space and starts building vertically. This enables far more apartments, offices and people per square mile, while avoiding the increased infrastructure costs of suburban sprawl. Semiconductors are evolving in much the same way. Moore’s Law is slowing, and adoption of new advanced technology nodes is slowing as wel... » read more

Software-Hardware Co-Design Becomes Real
By Brian Bailey - 27 Sep, 2021 - Comments: 0

For the past 20 years, the industry has sought to deploy hardware/software co-design concepts. While it is making progress, software/hardware co-design appears to have a much brighter future. In order to understand the distinction between the two approaches, it is important to define some of the basics. Hardware/software co-design is essentially a bottom-up process, where hardware is deve... » read more

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