Faster Verification Debug With AI


Every stage of semiconductor development takes longer and requires more effort with each new generation of chips. At no stage is this more apparent than functional verification. Industry consensus is that verification consumes roughly two-thirds of development time and resources. Within verification, debug is the most challenging step, consuming a third to two-thirds of the effort. Any serious ... » read more

Wafer-Scale vs. Chiplets: The New War? Part 1


Cerebras’ IPO is a meaningful moment for the semiconductor industry — and not just for the financial implications. Their confidence in their opening price reflects something the industry has effectively acknowledged: incremental chip scaling can no longer keep pace with what AI infrastructure demands. Radical approaches are earning serious consideration and serious capital. Cerebras... » read more

The Shape Of Prompts: Exploring Their Effect On Inference Infrastructure


AI inference prompts exhibit a shape-shifting behavior, arriving in many forms and attempting to fit themselves within the constraints of the inference stack. Ultimately, it is the design of the inference infrastructure that determines whether it can sustain a large volume of prompts or only a limited number. Prompts are not uniform transactions; they represent dynamic workload profiles whose ... » read more

A Bench-To-In-Field Telemetry Platform For Data Center Power Management


By Aakash Jani and Venkatesh Santhanagopalan NVIDIA's Blackwell platform delivered roughly 15% lower energy and 13% higher throughput [1]. Those gains came from hardware-firmware co-design that matches operating points to each workload, not a new process node. Most SoCs do not adapt: their margins are set and frozen the day silicon ships, based on the workloads measured at the bench. The mi... » read more

A Scalable Answer To Advanced-Node Characterization


If you're working on standard-cell libraries at 28 nm or below, you already know the math isn't in your favor. At the 130 nm node, a typical library had fewer than 100 cells and a handful of PVT corners. Fast-forward to 16/14 nm and beyond, libraries now contain 1,200+ cells across 200+ PVT corners. Every new SoC tape-out demands broader coverage for design robustness, and the characte... » read more

Overcoming Bottlenecks In Data Movement


AI is all about data. There is more data to process, store, and move, and more tradeoffs required to do that efficiently and with enough flexibility to handle changes in future workloads. Nandan Nayampally, chief commercial officer at Baya Systems, talks about networks on chip and networks across chip, what the choke points are for data movement, and where and when data coherency makes sense. » read more

Deterministic, Solver-Accurate Thermal and Warpage Analysis at Manufacturing Resolution for Advanced 2.5D HBM Packages


Thermal management has become the defining bottleneck in high-performance computing (HPC) and AI accelerator packaging. Modern packages integrate high-power ASICs with multiple High Bandwidth Memory (HBM) stacks on a silicon interposer, creating tightly coupled thermal and mechanical interactions. Die-to-die thermal crosstalk elevates HBM junction temperatures, while coefficient of thermal e... » read more

Rethinking AI-Scale Data Center Validation


The rapid growth of AI workloads is transforming AI data center networking, exposing critical limitations in traditional Ethernet validation and network testing methodologies. As data centers adopt 1.6T Ethernet, 224G SerDes and optical lanes, and tightly coupled GPU fabrics, networks must deliver ultra-high bandwidth, low latency, and predictable performance under dynamic east-west traffic con... » read more

Blog Review: May 27


Cadence's Igor Krause explains Precision Time Measurement (PTM), a PCIe feature that enables precise coordination of events across multiple components with independent local time clocks. Siemens' John McMillan suggests the way to achieve trusted traceability across the semiconductor supply chain is by implementing a blockchain-based distributed ledger paired with a secure digital twin. Sy... » read more

Multiphysics Fusion Technology for Multi-Die Designs Explained


Multiphysics issues are no longer a late-stage problem. Multi-die designs introduce tightly coupled electrical, thermal, electromagnetic, and electromechanical challenges that impact performance and reliability. This eBook shows why multiphysics analysis must move earlier in the design flow, and how a unified approach enables continuous validation from exploration through signoff. What You�... » read more

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