Design And Verification Issues In 2024


At the end of each year, I look back over the stories published and those that top the charts in terms of readership. I concentrate on those stories that are about the EDA tools and flows and the factors that are influencing them. These are good indicators of the problems designers and verification teams are facing today, and where they are looking for answers. This year's leading categories... » read more

Introduction Of High Bandwidth Embedded USB2v2 (eUSB2v2) Standard


Universal Serial Bus (USB) technology is the most popular connector in every computing device, but when it comes to embedded applications, where only a specific device function may be required, the architectural philosophy of the USB technology becomes inefficient. One example could be USB cameras. With increasing user expectations of camera resolution and frame rates, the bandwidth constrai... » read more

Redefining XPU Memory For AI Data Centers Through Custom HBM4: Part 3


This is the third and final of a series from Alphawave Semi on HBM4 and gives and examines custom HBM implementations. Click here for part 1, which gives an overview of the HBM standard, and here for part 2, on HBM implementation challenges. This follows on from our second blog, where we discussed the substantial improvements high bandwidth memory (HBM) provides over traditional memory tec... » read more

Strain, Stress In Advanced Packages Drives New Design Approaches


Thermal and mechanical stresses are creating significant challenges in heterogeneous chiplet assemblies, increasing the time and cost required to work through all the possible physical effects, dependencies, and interactions, and driving demand for new tools. Unlike in the past, when various components were crammed into a planar SoC on a relatively thick substrate, the new substrates are bei... » read more

Why Circuit Designers And Test Engineers Need Impedance Analyzers


All engineers know resistance is usually bad news. It generates heat. It reduces efficiency. It wears out components and cuts operational lifetimes. However, resistance is not the only kind of opposition to the current. When more complex waveforms are involved (like in radio applications), the inductors and capacitors contribute a different kind of opposition that is highly dynamic and compl... » read more

Enhancing Power Reliability Through Design-Stage Layout Optimization


As integrated circuit (IC) designs continue to scale, the demand for efficient power management, performance optimization and reliable physical layout modification grows more critical. Meeting these power, performance and area (PPA) targets is essential for ensuring that IC designs operate effectively at advanced process nodes. One of the main challenges for design and verification engineers is... » read more

Improving Verification Performance


Without methodology improvements, verification teams would not be able keep up with the growing complexity and breadth of the tasks assigned to them. Tools alone will not provide the answer. The magnitude of the verification task continues to outpace the tools, forcing design teams to seek out better ways to intermix and utilize the tools that are available. But as verification teams take on... » read more

2024 Set The Stage For NoC Interconnect Innovations In SoC Design


What a year it’s been for Arteris! Reflecting on 2024, the company achieved exciting milestones and breakthroughs that pushed the boundaries of system-on-chip (SoC) design. A game-changing new technology was unveiled, a major product was launched, and existing solutions were tailored for AI, automotive, high-performance computing (HPC) and more. Along the way, we welcomed new partners and ... » read more

SLM Evolves Into Critical Aspect Of Chip Design And Operation


Silicon lifecycle management has evolved greatly in the past five years, moving from novel concept to a key part of design flows at industry leaders such as NVIDIA, Amazon Web Services, Ericsson, and others. Along with becoming a major focus for companies developing semiconductors, the use cases have expanded. While initially focused on post-silicon insights, SLM has expanded to cover the en... » read more

Achieving Successful Multi-Die Signoff


Multi-die designs leveraging 2.5D and 3D technologies are becoming crucial for various electronics applications, including high-performance computing (HPC), artificial intelligence (AI), automotive, and mobile devices. These designs allow the integration of dies from different foundries and technology nodes, enhancing density and interconnect speeds beyond traditional discrete dies. However, th... » read more

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