category: System-Level Design

category: Auto, Security & Edge AI

How Wireless Coexistence Testing Exposes Real‑World Medical Device Behavior
By Joo-Ann Beh - 23 Jul, 2026 - Comments: 0

Modern medical devices rely on wireless connectivity to support alarms, clinician workflows, and continuous patient monitoring. Some wireless performance issues appear intermittently and only under specific interference conditions. These behaviors can be hard to reproduce late in development or after deployment. Coexistence testing provides a structured way to reveal and understand these failur... » read more

Accelerating AMS Verification With Mixed-Signal Visualizer
By Siemens EDA - 23 Jul, 2026 - Comments: 0

Debugging now consumes approximately 47 percent of integrated circuit (IC) verification time due to increasing semiconductor design complexity. Analog mixed-signal (AMS) verification presents unique challenges, as engineers must correlate continuous analog behavior with discrete digital logic across multiple abstraction levels, hierarchical configurations, and voltage domains. Traditional wa... » read more

Using Reliability Degradation Parameters To Drive Better Design Choices
By Niyati Singh - 23 Jul, 2026 - Comments: 0

A circuit can look perfect on day one and still drift out of specification after months or years of electrical and thermal stress. That is the reliability problem in a nutshell: the design does not only need to work when devices are fresh; the design must continue to meet performance expectations as devices age. A useful real-life analogy is a new car engine. A day-one test tells whether the... » read more

Bringing Design Data Management into the Developer Workflow
By Keysight - 22 Jul, 2026 - Comments: 0

As digital design workflows increasingly center on modern, text-based development environments, engineers expect the same efficiency from design data management as they do from coding tools. Visual Studio Code (VS Code) has become a preferred platform for developing RTL, HDL, scripts, and verification assets, offering a flexible and extensible workspace that streamlines day-to-day engineering t... » read more

Blog Review: July 22
By Jesse Allen - 22 Jul, 2026 - Comments: 0

Synopsys' Dana Neustadter and Ilya Tolchinsky warn that physical AI creates a different kind of security challenge that requires continuous runtime assurance to ensure outputs remain within safe operating bounds as conditions change. Cadence's Hamid Shojaei argues that building a reliable agent for chip design relies on closing the loop, where the agent proposes something, a tool gives it ... » read more

Enabling Comprehensive CWE-based Assurance for RISC-V Processors
By Arteris - 22 Jul, 2026 - Comments: 0

Abstract This paper presents a scalable, Common Weakness Enumeration (CWE)–based security assurance methodology for third-party RISC-V processor IP, developed collaboratively by Cycuity, BAE Systems, and SiFive. The approach adapts the MITRE Corporation CWE framework to systematically derive security requirements, verification properties, and evidence for RISC-V cores treated as third-party ... » read more

Silicon Starts with Proven IP: eBook
By Synopsys - 22 Jul, 2026 - Comments: 0

AI-driven complexity and advanced nodes are increasing silicon design risk and time pressure. This ebook shows why IP strategy is now an architectural decision and how silicon-proven IP reduces integration risk, improves first-pass success, and accelerates time-to-market. Learn how a unified portfolio of foundation, interface, and security IP enables scalable, high-performance designs acr... » read more

Verifying Networks On Chip
By Ed Sperling - 20 Jul, 2026 - Comments: 0

More data, more processing elements, and more memories are making it much harder to maintain consistent throughput in a multi-die assembly. There is more concurrent traffic, more potential interactions, and more protocol layers. Ashish Darbari, CEO of Axiomise, talks about the of coherency on serialization bugs, how to ensure data is secure, and how to ferret out the root cause of problems like... » read more

Data Center Chokepoints Tied To AI, Political Pressure, Supply Chain
By Brendan Heffernan - 20 Jul, 2026 - Comments: 0

Key Takeaways: AI-driven compute demands have led to several distinct supply chain bottlenecks for data centers. With data center energy demand surging faster than the grid can scale, small nuclear power has quickly moved to the center of the conversation. Hyperscalers have leaned into specialized facility design to meet their challenges, leading to an increasingly fragmented semicon... » read more

Blog Review: July 15
By Jesse Allen - 15 Jul, 2026 - Comments: 0

Cadence's Anupriya K explains how Address Translation Services (ATS) acts as the fast lane for PCIe memory access by caching address translations directly on the device and what makes it one of the toughest verification problems to solve. Synopsys' Greg Sorber considers the economic potential of physical AI and the impact that embedding intelligence into robots, vehicles, and equipment will ... » read more

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