How Far Left Can You Shift?


More steps in the design flow are shifting left, which makes a complicated design process even more complex. This includes early software prototyping, workload mapping, verification, multi-physics integration, verification, IP qualification. Frank Schirrmeister, executive director of strategic programs for System Solutions at Synopsys, talks about the increasing number of steps, the potential t... » read more

Continuous Physics Reasoning:
Definition, Minimum Criteria, and the Role of Foundation Models for Physics


Abstract Physical products are increasingly constrained by thermal, mechanical, electrical, and manufacturing realities, yet much of industry still relies on intermittent, expert-mediated physics evaluation. As systems become more complex and tightly coupled, this limits not only product development, but also manufacturing readiness, operational efficiency, and lifecycle performance. This p... » read more

UCIe vs. BoW: Practical Insights For Choosing The Right Chiplet Standards


As chiplet-based architectures gain traction across high-performance and cost-sensitive semiconductor applications, selecting the appropriate die-to-die interconnect standard has become a critical design decision. This white paper presents a practical, engineering-focused comparison of Universal Chiplet Interconnect Express (UCIe) and Bunch of Wires (BoW), highlighting their differing philosoph... » read more

Automate the Pain Away: HW/SW Interface Design Methodology


As System-on-Chip (SoC) designs become increasingly complex, engineering teams face growing challenges coordinating hardware and software development across multiple domains. Today's projects require more than isolated point tools — they demand connected methodologies that streamline workflows from system architecture and assembly through software enablement, validation, and implementatio... » read more

Optimizing Curvilinear OPC: Vector- Based Site and Anchor Decoupling


As semiconductor technology advances to sub-5 nm nodes, curvilinear mask features are essential for pattern fidelity but challenge traditional OPC methods. Siemens introduces an advanced vector-based site and anchor decoupling framework that independently and dynamically controls OPC fragmentation and optimization. This innovation significantly boosts process window robustness, speeds up mask r... » read more

Blog Review: June 24


Cadence's Veena Parthan shows how finite element analysis simulations for crash testing can surpass the limitations of physical testing and offer insights into a wider array of crash scenarios that were once impossible to explore. Siemens' Haitham Eissa and Amr Khafagy warn that once-passive dummy fill structures have begun to influence design performance significantly as the industry progre... » read more

Signoff Of Synthesis-Optimized Registers


How do you know when you sign off on a complex chip design that everything is going to work? There are more variables, more elements that need to be verified, and more waivers that need to be generated. Suresh Barla, senior director of field applications at Synopsys, talks about how to ensure that RTL is fully optimized for PPA targets in large designs that can include hundreds of millions of g... » read more

Designing Chips That Can Explain Themselves


Key Takeaways: On-die telemetry gives architects a path to replace worst-case design margin with measured silicon behavior, improving PPA without compromising resilience. As monitor density and control-loop speed increase, observability must be architected hierarchically across local hardware response, on-die processing, and fleet-level learning. The real payoff is architectural: str... » read more

Blog Review: June 17


Cadence's Rajan Jani explains NVMe's Controller Memory Buffer feature, which exposes on-controller memory directly to the host system to reduce latency, improve PCIe fabric efficiency, and increase performance in multi-switch topologies. Siemens' Linus Tauro shares how to run an SSN datapath at double the I/O data rate by implementing a BusFrequencyMultiplier and BusFrequencyDivider pair. ... » read more

Building Multi-Agent Systems For ASIC Flows


If one AI agent can solve a problem in a certain amount of time, can multiple agents solve it faster? The answer is yes, but only if the agents have well-defined roles and targets. This is where orchestrators fit in, and why they are so critical to agentic AI. Kexun Zhang, head of research at ChipAgents, talks about what exactly AI agents are, how they can be used to solve big problems that wou... » read more

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