category: System-Level Design

category: Auto, Security & Edge AI

AI In Chip Design: Lots Of Promise, Plenty Of Unanswered Questions
By Ed Sperling - 15 Jul, 2026 - Comments: 0

Key Takeaways: AI opens the door to exploring a much larger solution space, similar to what high-level synthesis did years ago, but questions persist about the impact of increasing reliance on what is essentially a black-box chip design. There is no consistent answer to how successful AI will be, where it will succeed or fail, or how it will apply to different markets and EDA customers.... » read more

Startup Funding: Q2 2026
By Jesse Allen - 13 Jul, 2026 - Comments: 0

Investors kept pouring money into AI hardware startups in the second quarter of 2026. While companies focused on chips for AI data centers have largely dominated the funding over the past year, startups creating edge silicon re-emerged this quarter as investors see the appeal of physical AI and real-time on-device applications. However, large-scale AI infrastructure chips and other attendant as... » read more

Change Is Tough
By Brian Bailey - 13 Jul, 2026 - Comments: 1

When I was actively involved in the creation of standards for the EDA and semiconductor industry, it was often joked that the great thing about standards is that there are plenty to choose from. According to the Internet, this quote can either be attributed to Grace Murray Hopper (an incredible pioneer in the development of modern programming languages and a rear admiral in the Navy), or Andrew... » read more

Blog Review: July 8
By Jesse Allen - 08 Jul, 2026 - Comments: 0

Synopsys' Greg Sorber finds that an explosion in product complexity has made it increasingly difficult to isolate decisions or defer validation until late in the development process, fundamentally changing how systems ranging from cars to consumer electronics are designed. Cadence's Harinee Rathod shows how MACsec helps ensure data confidentiality, integrity, and authenticity directly at the... » read more

Observability Is A Missing Layer In AI-Era Chiplet Design
By Ann Mutschler - 01 Jul, 2026 - Comments: 0

Key Takeaways: In chiplet-based architectures, observability must be designed as a fabric-aligned, cross-die telemetry plane so architects can correlate traffic, latency, congestion, and fault behavior across package boundaries without losing system context. AI can extract value from high-volume silicon telemetry only when the architecture provides consistent instrumentation, near-senso... » read more

Blog Review: July 1
By Jesse Allen - 01 Jul, 2026 - Comments: 0

Cadence's Krunal Patel highlights auto-negotiation, a foundational feature in Ethernet that allows two connected devices to automatically determine the best possible operating parameters for a link, eliminating manual configuration and ensuring optimal performance. Synopsys' Sumit Vishwakarma warns of the rising cost of overdesign, particularly in advanced node and multi-die designs, and how... » read more

Rethinking Chip Verification
By Ann Mutschler - 29 Jun, 2026 - Comments: 0

Key Takeaways: AI and modern tools are easing traditional verification pain, but they're not addressing the underlying bottleneck in complex designs. Work is underway to create a golden, unambiguous spec above RTL, tracing requirements from spec to implementation to verification and checking for gaps, conflicts, and inconsistencies across levels and blocks, often with AI help. Tool c... » read more

I/O Design Challenges Grow In AI Data Centers And HPC Clusters
By Liz Allan - 25 Jun, 2026 - Comments: 0

Key Takeaways: A designer’s choice of I/O connectors and interconnect protocols can be the difference between a massively profitable AI chip and a flop. I/O tradeoffs impact airflow, cooling, rack design, power coming into the rack, and other critical aspects of HPC chip design. Reliability is paramount, so standards must be followed, and I/Os need redundant pins. Other innovations... » read more

Verification Methodologies Struggle To Keep Up With AI
By Brian Bailey - 25 Jun, 2026 - Comments: 0

Key Takeaways:  The rapid development of AI has resulted in new capabilities being provided to verification teams, beyond their ability to rationally insert them into accepted methodologies.  There is a lot of uncertainty about who will benefit the most from this technology. Is AI a junior engineer replacement or an enhancer?  The biggest benefits will come when AI helps engineers... » read more

Executive Outlook: Agentic AI’s Impact On Chip Design
By Ed Sperling - 25 Jun, 2026 - Comments: 1

Key Takeaways: Agentic AI has the potential to make engineers more productive, speed time to market, and automate some of the drudge work. The big challenge for design and verification engineers is where and whether they trust AI to get everything right, because there is no margin for error in semiconductors. Having humans in the loop will likely be the rule rather than the exception... » read more

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