Optimizing Data Movement


Demand for new and better AI models is creating an insatiable demand for more processing power and much better data throughput, but it's also creating a slew of new challenges for which there are not always good solutions. The key here is figuring out where bottlenecks might crop up in complex chips and advanced packages. This involves a clear understanding of how much bandwidth is required ... » read more

Boosting AI Performance With CXL


As AI applications rapidly advance, AI models are being tasked with processing massive amounts of data containing billions – or even trillions – of parameters. Each large workload involves numerous iterations for data comparison, predictive calculations, and parameter results updating during training. Hence, there is a constant demand for flexible memory expansion and memory sharing among d... » read more

A Balanced Approach To Verification


First-time chip success rates are dropping, primarily due to increased complexity and attempts to cut costs. That means management must take a close look at their verification strategies to determine if they are maximizing the potential of their tools and staff. Using simulation to demonstrate that a design exhibits a required behavior has been the cornerstone of functional verification sinc... » read more

Executive Outlook: Chiplets, 3D-ICs, and AI


Semiconductor Engineering sat down to discuss chiplets and the challenges of moving to 3D-ICs with Bill Mullen, Ansys fellow; John Ferguson, senior director of product management at Siemens EDA; Chris Mueth, senior director of new markets and strategic initiatives at Keysight; Albert Zeng, senior engineering group director at Cadence; Anand Thiruvengadam, senior director and head of AI product ... » read more

Thermo-Mechanical Stress On Active Chiplets In A 3D-IC Heterogeneous Package Assembly


The move to heterogeneous multi-chip/chiplet products improves yield, performance and modularity while reducing power and overall product footprint. However, this shift to heterogeneous assembly also introduces new complexities that can influence chip warpage and circuit behavior due to thermo-mechanical stress impacts. In heterogeneous 3D IC architectures, the interaction between the chips ... » read more

CSR Management: Life Beyond Spreadsheets


The ASIC, ASSP, and system-on-chip (SoC) design landscape has undergone significant evolution over the past two decades. For example, while early devices contained only tens of intellectual property (IP) blocks, modern high-end SoCs may integrate up to 1000 IPs, each containing millions of logic gates. Furthermore, unlike their predecessors, today’s SoCs are no longer primarily hardware; i... » read more

Optical Interconnectivity At 224 Gbps


AI is generating so much traffic that traditional copper-based approaches for moving data inside a chip, between chips, and between systems, are running out of steam. Just adding more channels is no longer viable. It requires more power to drive signals, and the distance those signals can travel without excessive loss is shrinking. Mike Klempa, product marketing specialist at Alphawave Semi, di... » read more

SoC Power Delivery Network (PDN) Telemetry And Applications


PDN characterization needs visibility at the transistor. Through this white paper, we will learn why PDN visibility is crucial to each stage of the silicon lifecycle and its relation to power, performance, and in-field uptime. Register here to download the paper. » read more

AI Infrastructure: Optimized For Model Training


This white paper discusses the critical infrastructure needed for efficient AI model training, emphasizing the role of network capabilities in handling vast data flows and minimizing delays. It outlines challenges in model training and innovative solutions that can enhance performance. AI Revolution: The increasing complexity of AI applications, such as autonomous vehicles and personalized m... » read more

Mastering AI Chip Complexity: Your Guide to First-Pass Silicon Success


This eBook provides a resource for innovators in the fast-changing realm of AI chip development. It delves into the opportunities and challenges of designing cutting-edge AI chips and chiplets, focusing on the transition from traditional monolithic architectures to multi-die and chiplet-based solutions. The content covers essential topics such as architectural exploration, silicon design, a... » read more

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