category: System-Level Design

category: Auto, Security & Edge AI

Creating Agentic EDA Methodologies
By Brian Bailey - 30 Apr, 2026 - Comments: 1

Key takeaways Agentic methodologies need to be able to reason across multiple data formats and abstractions. It is not clear how much data from previous designs is useful in new designs. Standards may help, but the lack of them may only impact cost. The relationship between tools and methodologies is bidirectional. Tools enable methodologies, and methodologies are dependent ... » read more

Foundry Capacity Is Limiting Who Competes At Leading Edge Nodes
By Ann Mutschler - 30 Apr, 2026 - Comments: 0

Key Takeaways: Leading-edge node access is increasingly reserved for hyperscalers, squeezing smaller chip developers. Chiplets and advanced packaging offer a path forward, but raise cost, complexity, and risk — especially for smaller teams. Chip architecture is now driven as much by capacity, yield, and economics as by technical goals. The benefits of device scaling are sl... » read more

Unlocking High-Speed Serial Link Signal Integrity With AMI Model
By Priyadarshini N D - 30 Apr, 2026 - Comments: 0

As the demand for faster data rates in high-speed interfaces such as PCIe, USB, and DDR continues to escalate, maintaining signal integrity has become a significant challenge for engineers. Traditional SPICE-based simulations, while precise, often suffer from computational intensity, making it impractical to model the intricate behavior of high-speed signals across millions of bits. This is ... » read more

Facilitating Complex SoC Design Through Automation And Integration
By Andy Nightingale - 30 Apr, 2026 - Comments: 0

The design demands of today’s highly advanced system-on-chip (SoC) devices have long outgrown the capabilities of manual workflows to manage them effectively. As these chips become more complex, only sophisticated, high-performance, and scalable automation can ensure that every component of the SoC functions seamlessly. The SoC integration challenge A fundamental aspect of SoC design is the... » read more

How To Streamline Your Advanced Package Interconnect Designs
By Maria Castillo - 30 Apr, 2026 - Comments: 0

Monolithic system-on-chip (SoC) designs was once a popular choice. However, they face significant constraints in the era of AI. By forcing all chip functions into a single die and process node, they reduce engineering, manufacturing, and design cost flexibility. In contrast, the multi-die nature of chiplets enables different SoC functions to be designed and verified independently and fabrica... » read more

Solving Clock Signal Integrity And Jitter Issues
By Manoz Palaparthi - 30 Apr, 2026 - Comments: 0

A recent blog post discussed the challenges of clock signal integrity and clock jitter in deep submicron semiconductor devices. Nice, clean clock signals are degraded due to many factors, including noise in the power delivery network (PDN). Timing variation due to clock jitter is also a serious issue, especially for chips operating at low voltage with high frequencies. The impact due to cloc... » read more

From Standards To Systems: The Chiplet Era On Arm
By Nandan Nayampally - 30 Apr, 2026 - Comments: 0

For three decades, Arm didn’t just participate in industry transformation — it redefined it. From mobile to cloud to automotive, Arm’s architecture and the AMBA ecosystem have become the backbone of scalable compute. Now the industry faces its next structural shift: The era of monolithic SoCs is tapering and giving way to the era of chiplet systems. While complex SoCs are going to b... » read more

NoC Coherency Challenges Balloon With AI SoCs And Chiplets
By Liz Allan - 30 Apr, 2026 - Comments: 0

Key Takeaways Data movement, congestion, and energy efficiency are key determiners of whether compute is usable. Different processors bring various coherency challenges. For example, a cache-coherent NoC for CPUs is expensive and harder to verify than an I/O-coherent NoC for an accelerator. Designers need to balance top-down performance with bottom-up physical engineering to effect... » read more

Assuring Comprehensive Security Coverage In Hardware Design
By Arteris - 29 Apr, 2026 - Comments: 0

Is your hardware design prepared to withstand today’s complex threat landscape? Verifying the effectiveness of security functionality and protections is essential to safeguarding your designs. By adopting a systematic framework and measuring coverage throughout the pre-silicon development cycle, you can proactively identify vulnerabilities and strengthen your hardware’s resilience. Downl... » read more

Blog Review: Apr. 29
By Jesse Allen - 29 Apr, 2026 - Comments: 0

Synopsys' Madhumita Sanyal shows why interface IP has emerged as the keystone for building scalable, reliable 3D multi-die designs in which interconnects often have a greater influence on overall system capability than the peak performance of individual dies. Cadence's Frank Ferro checks out why SOCAMM2 built on LPDDR is being deployed in AI data centers, increasing memory bandwidth and capa... » read more

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