category: System-Level Design

category: Auto, Security & Edge AI

Automate the Pain Away: HW/SW Interface Design Methodology
By Arteris - 24 Jun, 2026 - Comments: 0

As System-on-Chip (SoC) designs become increasingly complex, engineering teams face growing challenges coordinating hardware and software development across multiple domains. Today's projects require more than isolated point tools — they demand connected methodologies that streamline workflows from system architecture and assembly through software enablement, validation, and implementatio... » read more

Optimizing Curvilinear OPC: Vector- Based Site and Anchor Decoupling
By Siemens EDA - 24 Jun, 2026 - Comments: 0

As semiconductor technology advances to sub-5 nm nodes, curvilinear mask features are essential for pattern fidelity but challenge traditional OPC methods. Siemens introduces an advanced vector-based site and anchor decoupling framework that independently and dynamically controls OPC fragmentation and optimization. This innovation significantly boosts process window robustness, speeds up mask r... » read more

Blog Review: June 24
By Jesse Allen - 24 Jun, 2026 - Comments: 0

Cadence's Veena Parthan shows how finite element analysis simulations for crash testing can surpass the limitations of physical testing and offer insights into a wider array of crash scenarios that were once impossible to explore. Siemens' Haitham Eissa and Amr Khafagy warn that once-passive dummy fill structures have begun to influence design performance significantly as the industry progre... » read more

Signoff Of Synthesis-Optimized Registers
By Ed Sperling - 17 Jun, 2026 - Comments: 0

How do you know when you sign off on a complex chip design that everything is going to work? There are more variables, more elements that need to be verified, and more waivers that need to be generated. Suresh Barla, senior director of field applications at Synopsys, talks about how to ensure that RTL is fully optimized for PPA targets in large designs that can include hundreds of millions of g... » read more

Designing Chips That Can Explain Themselves
By Ann Mutschler - 17 Jun, 2026 - Comments: 1

Key Takeaways: On-die telemetry gives architects a path to replace worst-case design margin with measured silicon behavior, improving PPA without compromising resilience. As monitor density and control-loop speed increase, observability must be architected hierarchically across local hardware response, on-die processing, and fleet-level learning. The real payoff is architectural: str... » read more

Blog Review: June 17
By Jesse Allen - 17 Jun, 2026 - Comments: 0

Cadence's Rajan Jani explains NVMe's Controller Memory Buffer feature, which exposes on-controller memory directly to the host system to reduce latency, improve PCIe fabric efficiency, and increase performance in multi-switch topologies. Siemens' Linus Tauro shares how to run an SSN datapath at double the I/O data rate by implementing a BusFrequencyMultiplier and BusFrequencyDivider pair. ... » read more

Building Multi-Agent Systems For ASIC Flows
By Ed Sperling - 10 Jun, 2026 - Comments: 0

If one AI agent can solve a problem in a certain amount of time, can multiple agents solve it faster? The answer is yes, but only if the agents have well-defined roles and targets. This is where orchestrators fit in, and why they are so critical to agentic AI. Kexun Zhang, head of research at ChipAgents, talks about what exactly AI agents are, how they can be used to solve big problems that wou... » read more

Disturbance In Verification
By Brian Bailey - 08 Jun, 2026 - Comments: 3

When writing my recent story about agentic verification, there was one quote from Abhi Kolpekwar, senior vice-president and general manager at Siemens EDA, that really struck a chord. He was talking about the additional token costs that would be consumed when a verification engineer starts asking the agents to do what was considered to be part of their job. "Consider the total cost of owners... » read more

Blog Review: Jun. 3
By Jesse Allen - 03 Jun, 2026 - Comments: 0

Siemens' Gordon Allan contends that verification IP gives design teams a practical way to verify standards-based interfaces and memories without rebuilding the same infrastructure generation after generation and shares key evaluation metrics. Synopsys' Sutirtha Kabir suggests that successful multi-die design will require deeper collaboration from early architecture exploration to manufacturi... » read more

The Evolution Of UCIe
By Ed Sperling - 02 Jun, 2026 - Comments: 0

Since it was released in March 2022, the Universal Chiplet Interconnect Express (UCIe) has grown from a basic way of connecting two dies together into a comprehensive specification that can ensure the handoff of data between various components in an advanced package, as well as validate the chiplets within that package. Mayank Bhatnagar, director of product marketing at Cadence, talks about the... » read more

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