Blog Review: Jun. 3

Siemens’ Gordon Allan contends that verification IP gives design teams a practical way to verify standards-based interfaces and memories without rebuilding the same infrastructure generation after generation and shares key evaluation metrics.

Synopsys’ Sutirtha Kabir suggests that successful multi-die design will require deeper collaboration from early architecture exploration to manufacturing and test, coupled with continuous verification and explainable AI.

Cadence’s Vanessa Do points to unordered I/O, which allows devices to determine when ordering is unnecessary, as key for enabling AI training and inference workloads to fully utilize PCIe 7.0’s increased bandwidth with higher parallelism and lower latency.

Keysight’s Simon Rance warns that scattered, duplicated, poorly governed, or hard to access data is hampering efforts to deploy AI for semiconductor design.

Lam Research’s QingPeng Wang explains how digital twins combined with machine learning allow engineers to minimize costly wafer experiments and simultaneously mitigate multiple failure modes by simulating the entire GAA logic process upfront.

Arm’s Fidel Makatia introduces an open-source project that uses edge AI to provide low-latency, offline sign language-to-text translation with on-device privacy and lower communication barriers in healthcare, education, and public services.

SEMI’s Paul Trio shares updates related to flexible hybrid electronics standardization, including a reliability guide, substrate mapping revisions, and robot-based maintenance solutions.

Plus, check out the blogs featured in the latest Systems & Design newsletter:

Axiomise’s Ashish Darbari and Bing Xue show how to ferret out deep corner cases that can cause deadlocks and silent data corruption.

Siemens EDA’s Rory Riggs explains the need to look beyond traditional spacing and distance checks for electrical verification and sign-off of PCBs.

Arteris’ Andy Nightingale looks at the impact of workloads on interconnects.

Vinci’s John Bruggeman explains why continuous validated physics reasoning is essential in the engineering workflow.

Synopsys’ Taruna Reddy shows the benefits of automating a wide range of debug tasks, such as waveform inspection, logfile analysis, and source code navigation.

Baya Systems’ Nandan Nayampally zeroes in on Cerebras’ chip and how it broke all the rules for design.

Keysight’s Amritam Putatunda looks at how to balance GPU, memory, storage, and network resources in AI inference infrastructure.

Movellus’ Aakash Jani and Venkatesh Santhanagopalan explain how to optimize SoCs to run at their true power and performance limits throughout the full system lifecycle.

Cadence’s Rajshekharayya Hiremath describes a scalable path for multi-PVT library characterization as cell and corner counts increase.