Blog Review: June 17

Cadence’s Rajan Jani explains NVMe’s Controller Memory Buffer feature, which exposes on-controller memory directly to the host system to reduce latency, improve PCIe fabric efficiency, and increase performance in multi-switch topologies.

Siemens’ Linus Tauro shares how to run an SSN datapath at double the I/O data rate by implementing a BusFrequencyMultiplier and BusFrequencyDivider pair.

Synopsys’ Achim Nohl, Buvanesh Balasubramanian, Daniel Castelló, and Varun Shah consider how to adapt Git-based collaboration, CI/CD practices, GitHub pull requests, and agentic workflows for chip RTL, verification, and integration flows.

Arm’s Idit Diamant and colleagues improved low-light image enhancement for real-world AI vision systems using a generative AI technique called latent flow matching that enables the model to learn a structured restoration process rather than applying a direct brightness adjustment.

Keysight’s Liang Kan and Eric Yu explore some of the challenges involved in testing AI network fabrics and why micro-benchmarks aren’t enough for production-ready networks.

In a blog for SEMI, JST’s Ismail Kashkoush highlights the critical role of wet processing in photonics manufacturing, with cleaning, etching, and drying steps each having a direct impact on surface quality, defectivity, and optical performance.

Plus, check out the blogs featured in the latest Automotive, Security & Edge AI, Test, Measurement & Analytics, and Low Power-High Performance newsletters:

Technology strategy advisor Geoff Tate finds that optical interconnects are needed to boost GPU throughput and utilization.

Siemens EDA’s Chun-hsiang Chang EDA explains how early schematic analysis can prevent late-stage rework.

Rambus’ Vincent van der Leest points to three protocols that form a coherent and scalable security architecture for terabit Ethernet.

Keysight EDA’s Jasper van Woudenberg shows why physical attack resistance must be validated rather than assumed.

Cadence’s Joe Chen stresses the need to replicate real-world operating conditions when stress testing PCIe.

Infineon’s Steve Hanna looks at how to mitigate the expected increase in smart home vulnerability alerts, software updates, and breaches.

Synopsys’ Andrew Appleby, Daryl Seitzer, and Nafiz Ahmed detail how to reduce risk and improve outcomes during complex technology node transitions.

Synaptics’ Karthikeyan Shanmuga Vadivel and Sauryadeep Pal dig into why modern edge devices demand heterogeneous AI architectures that can mix and match subsystems to accelerate different aspects of inferencing.

Imagination’s Ke Xu predicts that combining compute, AI, and graphics will become a key differentiator for platform competitiveness.

PDF Solutions’ Ming Zhang contends that advanced node manufacturing and heterogeneous integration require partnerships that span the full value chain.

Onto Innovation’s Keira Lei argues that AI must operate as a verifiable engineering collaborator where outputs are transparent, traceable, and subject to human interpretation and refinement.

Synopsys’ Ash Patel and Shubharthi Datta and Cisco’s Chuanyun Fan outline how PCI Express can enable faster, more scalable, and lifecycle-wide testing while conserving limited pins.

Siemens EDA’s Peter Orlando emphasizes that in-field testing is essential for quickly detecting emerging defects throughout a device’s operational lifespan.

Nordson’s Chris Rand details how HBM’s 3D architecture — stacked DRAM dies interconnected via TSVs — delivers exceptional bandwidth and efficiency, but introduces new inspection and quality-assurance challenges.

Siemens EDA’s Matt Grange digs into thermal and mechanical issues in 2.5D and 3D-IC designs.

Rambus’ Carlos Weissenberg explains why tight coordination between clocking, power delivery, and system-level management is necessary at higher DDR5 data rates.

Expedera’s Sharad Chole examines packet-based architectures and how they can enable out-of-order execution to optimize hardware utilization without retraining the model.

Ayar Labs’ Nandita Aggarwal and Wiwynn’s Nicholas Chang discuss how co-packaged optics can deliver the bandwidth density and efficiency needed to scale AI compute clusters.

Cadence’s Shyam Sharma explores the new MRDIMM architecture that enables higher data rates and densities while remaining pin-compatible with traditional DIMM.

Synopsys’ Lakshmi Jain and Wei-Yu Ma look at a new approach for hybrid-bonded 3D integration.

Arm’s Odin Shen shows how developers can turn model experimentation into concrete observation of edge AI workloads across different scenarios.