DDR5 MRDIMM: A Transformational Evolution For DDR5 DIMM

DDR5 is the latest generation of DDR server memory capable of supporting data rates of up to 9,200 Mbps, which is a huge leap over the previous generation of DDR memories. It is used in a wide variety of applications, with the huge server and data center market being the key driver behind the adoption of DDR5-based memory systems. As systems move towards more CPU cores, bandwidth, and capacity, DDR5 is considered the most widely used DDR memory as compared to the previous generation, DDR4.

DDR memories are typically used as a part of dual in-line memory (DIMM) cards. DIMMs are a JEDEC-defined standard for increasing density and bus width by connecting several individual DRAM memories to a DIMM card. Traditionally, DIMMs can be categorized as Small Outline-DIMM/Unbuffered DIMM (uses just the DRAM memories), Registered DIMM (uses RCD + the DRAM), and Load Reduced DIMM (uses RCD + DRAM + DB).

The Registering Clock Driver (RCD) and Data Buffer (DB) help the RDIMM and LRDIMM with better Command/Clock and Data signal quality and help with Electrostatic Overstress (EOS) and electrostatic discharge (ESD) issues. However, even with these, bringing DDR5 LRDIMMs to support higher data rates has become a challenge beyond 4800 Mbps due to issues like clock loading.

To enable DDR5 DIMM in supporting higher speeds like 12,800 Mpbs, JEDEC members have produced a new architecture and a new category of DIMMs called Multiplexed Rank DIMM (MRDIMM). This is a paradigm shift for DDR memories that not only enables DDR5 DIMM to support DDR5 SDRAM’s current highest speeds of 9200 Mpbs but can also allow for higher data rates. Some of the key features for DDR5 MRDIMM Generation 2 are:

• For the first time, there will be two sets of clocks within the DIMM, including a Host side clock, which will run at twice the speed of the internal clock on which DRAMs will be operating. This will allow DRAM and DB’s DRAM side interface to only require meeting half-rate operating speed requirements.
• DDR5 MRDIMM will benefit from being able to support higher densities than traditional RDIMM/LR-DIMM, since it will have twice the number of DRAMs. These DRAMs are connected to support two Pseudo Channels for MRDIMMs, doubling the DIMM capacity.
• DDR5 MRDIMM is pin compatible with traditional DIMM, and it can be used in the same DIMM slots that are used for DDR5 RDIMMs.
• There is no change to the DRAMs used for DDR5 MRDIMM. DDR5 MRDIMM Generation 2 cards only require the use of new DDR5 MRCD and DDR5 MDB components and will use the same DDR5 SDRAM components.
• DDR5 MDB has two DRAM side interfaces named as the A and B sides. It multiplexes DRAM data and sends it to the Host in an interleaved pattern at twice the speed at which it is sampling Data from the DRAMs on its A and B sides.
• Unlike traditional DDR5 DIMMs that can only have two Physical Ranks, DDR5 MRDIMM is capable of supporting up to four physical ranks.
• While DDR5 MRDIMM is pin compatible with traditional DDR5 RDIMM and follows the same DDR5 protocol, the memory controller and PHY will still need changes to support MRDIMMs, such as changes in the training sequences, handling two sets of DRAMs connected to PS0/PS1, programming of additional RCD/DB Control words, supporting burst with twice the burst lengths, etc.
• DDR5 MRDIMM will have multiple generations, with Generation 2 supporting up to 12.8GT/s and Generation 3 supporting even higher data rates.

DDR5 MRDIMM is an evolving standard that is still in progress at JEDEC.

The Cadence memory model for DDR5/DDR5 DIMM aims to support all generations of DDR5 MRDIMM with Cadence DDR5 MRDIMM (including MRCD and MDB) VIPs feature tracking JEDEC DDR5 MRDIMM Generation 2 and Generation 3 Specification development.