tag: DIMM

DDR5 PMICs Enable Smarter, Power-Efficient Memory Modules
By Tim Messegee - 16 May, 2024 - Comments: 0

Power management has received increasing focus in microelectronic systems as the need for greater power density, efficiency and precision have grown apace. One of the important ongoing trends in service of these needs has been the move to localizing power delivery. To optimize system power, it’s best to deliver as high a voltage as possible to the endpoint where the power is consumed. Then a... » read more

IC Reliability Burden Shifts Left
By Ann Mutschler - 23 Jun, 2022 - Comments: 0

Chip reliability is coming under much tighter scrutiny as IC-driven systems take on increasingly critical and complex roles. So whether it's a stray alpha particle that flips a memory bit, or some long-dormant software bugs or latent hardware defects that suddenly cause problems, it's now up to the chip industry to prevent these problems in the first place, and solve them when they do arise. ... » read more

Multi-DRAM Memory Subsystems In SoCs
By Shyam Sharma - 14 Oct, 2021 - Comments: 0

Even with DRAM capacity going up with each generation of DRAM, the demand for memory densities by a variety of applications is growing at an even faster rate. To support these high memory densities and bus width requirements (that are typically more than what a single DRAM can support), almost all the new generation of memory subsystems and SoCs have multiple DRAM dies combined to effectively c... » read more

Architecting a Hardware-Managed Hybrid DIMM Optimized for Cost/Performance
By Rambus - 09 Jan, 2019 - Comments: 0

Authors: Fred Ware,(1) Javier Bueno,(2) Liji Gopalakrishnan,(1) Brent Haukness,(1) Chris Haywood,(1) Toni Juan,(2) Eric Linstadt,(1) Sally A. McKee,(3) Steven C. Woo,(1) Kenneth L. Wright,(1) Craig Hampel,(1) Gary Bronner.(1) (1) Rambus Inc. Sunnyvale, California (2) Metempsy, Barcelona, Spain (3) Clemson University, South Carolina Rapidly evolving workloads and exploding data volumes ... » read more

Enabling Higher System Performance With NVDIMM-N
By Sarvagya Kochak - 10 Aug, 2017 - Comments: 0

The shift from the traditional enterprise data center to the cloud is driving an insatiable demand for increased bandwidth and lower latencies. This is fundamentally reshaping traditional memory, storage, network and computing architectures. Although the semiconductor industry has been innovating to meet the needs of these new architectures, it continues to grapple with a waning Moore’s Law t... » read more

Memory Buffer Chips: Satisfying Amdahl’s Law To Sustain Moore’s Law
By John Eble - 13 Jul, 2017 - Comments: 0

Moore’s Law, the observation that the available transistors in an integrated circuit doubles every two years, has driven the semiconductor and IT industries to unparalleled growth over the last 50+ years. These transistors have been used in CPUs to increase the number of parallel execution units and instruction fetches, expand the levels of on-chip cache (and overall capacity), support spe... » read more

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