Architecting a Hardware-Managed Hybrid DIMM Optimized for Cost/Performance

Review a proposal for a hybrid DIMM architecture that uses a hardware-managed DRAM in front of enhanced flash.


Fred Ware,(1) Javier Bueno,(2) Liji Gopalakrishnan,(1) Brent Haukness,(1) Chris Haywood,(1) Toni Juan,(2) Eric Linstadt,(1) Sally A. McKee,(3) Steven C. Woo,(1) Kenneth L. Wright,(1) Craig Hampel,(1) Gary Bronner.(1)

(1) Rambus Inc. Sunnyvale, California
(2) Metempsy, Barcelona, Spain
(3) Clemson University, South Carolina

Rapidly evolving workloads and exploding data volumes place great pressure on data-center compute, IO, and memory performance, and especially on memory capacity. Increasing memory capacity requires a commensurate reduction in memory cost per bit. DRAM technology scaling has been steadily delivering affordable capacity increases, but DRAM scaling is rapidly reaching physical limits. Other technologies such as flash, enhanced flash, phase change memory, and spin torque transfer magnetic RAM hold promise for creating high capacity memories at lower cost per bit. However, these technologies have attributes that require careful management.

We propose a hybrid DIMM architecture that uses a hardware-managed DRAM in front of enhanced flash, which has much lower read latencies than conventional flash. We explore the design space of such SCM devices in the context of different technology parameters, evaluating performance and endurance for data-center workloads. Our hybrid memory architecture is commercially realizable and can use standard DIMM form factors, giving it a low barrier to market entry. We find that for workloads like media streaming, enhanced flash can be combined with DRAM to enable 88% of the performance of a DRAM-only system of the same capacity at 23% of the cost, even when factoring in replacement costs due to wear-out. The bottom line is that cost per performance is a factor of 3.8 better than DRAM.

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