Agile Standards


Semiconductor Engineering sat down with Lu Dai, chairman for Accellera and senior director of engineering at Qualcomm, to discuss what's changing in standards development. What follows are excerpts of that conversation. SE: Accellera has had a great first half of the year. Dai: Yes, we are only half way through the year and yet we got Portable Stimulus Standard (PSS) out, the SystemC CCI ... » read more

The PCB Engineer’s Guide To Successful DDR Bus Design


This paper tackles the critical signal integrity concerns encountered when designing, simulating, and analyzing DDR buses. The first section describes DDR bus design challenges that can be particularly problematic, even intimidating, to designers. Subsequent sections describe how simulation and analysis speed up the design of a functioning DDR system to reduce PCB spins and shorten the time to ... » read more

Tech Talk: eFPGA Acceleration


Achronix's Kent Orthner talks about when and why to use embedded FPGAs, and how they co-exist with—and compare to—other processing elements. [youtube vid=TXeIOmo7O9o] » read more

The Hunt For A Low-Power PHY


Physics has been on the side of chipmakers throughout most of the lifetime of [getkc id="74" comment="Moore's Law"], but when dealing with the world outside the chip, physics is working against them. Pushing data at ever-faster rates through boards and systems consumes increasing amounts of power, but the power budget for chips has not been increasing. Could chips be constrained by their int... » read more

HBM Upstages DDR In Bandwidth, Power


For graphics, networking, and high performance computing, the latest iteration of high-bandwidth memory (HBM) continues to rise up as a viable contender against conventional DDR, GDDR designs, and other advanced memory architectures such as the Hybrid Memory Cube. [getkc id="276" kc_name="HBM"] enables lower power consumption per I/O and higher bandwidth memory access with a more condensed f... » read more

Chip Advances Play Big Role In Cloud


Semiconductor engineering teams have been collaborating with key players in the data center ecosystem in recent years, resulting in unforeseen and substantial changes in how data centers are architected and built. That includes everything from which boxes, boards, cards and cables go where, to how much it costs to run them. The result is that bedrock communication technology and standards li... » read more

Oscilloscopes: The EE’s Stethoscope


Oscilloscopes are like the electricity to your house. You don't give it much thought until a storm knocks it out. The entire electronics industry can't function without oscilloscopes. But this equipment is such a constant and so consistent, we sometimes forget it's there. Semiconductor Engineering spent time with three Test & Measurement (T&M) industry stalwarts to talk about Oscillo... » read more

Time For A DDR Background Check


In this month’s blog we continue our discussion of power management, specifically looking at how architects can improve the energy efficiency of their SoC as it uses system memory. In March we teamed up with Micron, a global supplier of high performance, low power memory technologies, to present a tutorial at SNUG Silicon Valley (see proceedings) explaining the practical steps system desig... » read more

Advanced Analog And Mixed Signal Design Continues Pushing The Design Envelope


As PCB design has evolved into its present form with extremely complex boards housing high speed circuitry in very small areas, analog and mixed signal (AMS) and high speed analysis can address the latest design challenges. Analog/mixed signal design More and more products incorporate more than just digital circuitry. The vast majority of products now integrate digital and analog circuitr... » read more

Optimizing DDR Memory Subsystem Efficiency


The memory subsystem sits at the core of a System-on-Chip (SoC) platform and can make all the difference between a well-designed system meeting its performance requirements and a system that delivers poor performance, or even fails to operate correctly. State-of-the-art DDR memory controllers use advanced arbitration and scheduling policies to optimize DDR memory efficiency. At the same time, t... » read more

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