tag: DDR

DRAM Test And Inspection Just Gets Tougher
By Anne Meixner - 07 Nov, 2023 - Comments: 0

DRAM manufacturers continue to demand cost-effective solutions for screening and process improvement amid growing concerns over defects and process variability, but meeting that demand is becoming much more difficult with the rollout of faster interfaces and multi-chip packages. DRAM plays a key role in a wide variety of electronic devices, from phones and PCs to ECUs in cars and servers ins... » read more

Server Design With Pin-Efficient CXL Interface (Georgia Tech)
By Technical Paper Link - 10 May, 2023 - Comments: 0

A new technical paper titled "A Case for CXL-Centric Server Processors" was written by researchers at Georgia Tech. Abstract: "The memory system is a major performance determinant for server processors. Ever-growing core counts and datasets demand higher bandwidth and capacity as well as lower latency from the memory system. To keep up with growing demands, DDR--the dominant processor inter... » read more

Pinpointing Timing Delays Can Improve Chip Reliability
By Anne Meixner - 09 May, 2023 - Comments: 0

Growing pressure to improve IC reliability in safety- and mission-critical applications is fueling demand for custom automated test pattern generation (ATPG) to detect small timing delays, and for chip telemetry circuits that can assess timing margin over a chip's lifetime. Knowing the timing margin in signal paths has become an essential component in that reliability. Timing relationships a... » read more

How To Safeguard Memory Interfaces By Design
By Dana Neustadter - 06 Apr, 2023 - Comments: 0

By Dana Neustadter and Brett Murdock In 2017, the credit bureau Equifax announced that hackers had breached its system, unleashing the personal information of 147-million people. As a result, the company has settled a class action suit for $425 million to aid those impacted, including identity theft, fraud, financial losses, and the expenses to clean up the damage. Whether the threat is iden... » read more

CXL Memory: Detailed Characterization Analysis Using Micro-Benchmarks And Real Applications (UIUC, Intel Labs)
By Technical Paper Link - 30 Mar, 2023 - Comments: 0

A new technical paper titled "Demystifying CXL Memory with Genuine CXL-Ready Systems and Devices" was published by researchers at University of Illinois Urbana-Champaign (UIUC) and Intel Labs. Abstract: "The high demand for memory capacity in modern datacenters has led to multiple lines of innovation in memory expansion and disaggregation. One such effort is Compute eXpress Link (CXL)-based... » read more

Efficiently Process Large RM Datasets In Underlying Memory Pool, Disaggregated Over CXL (KAIST)
By Technical Paper Link - 29 Jan, 2023 - Comments: 0

A technical paper titled "Failure Tolerant Training with Persistent Memory Disaggregation over CXL" was published (preprint) by researchers at KAIST and Panmnesia. "TRAININGCXL can efficiently process large-scale recommendation datasets in the pool of disaggregated memory while making training fault tolerant with low overhead," states the paper. Find the technical paper here. or here (IEE... » read more

Jitter Budgeting For Clock Distribution Networks In High-Speed PHYs And SerDes
By Synopsys - 07 Dec, 2022 - Comments: 0

This paper presents a simple but practically precise estimation of periodic single-tone power supply induced jitter (PSIJ) for MOS clock buffer chains. The estimation is algebraically simple for its analytical closed-form expression requiring only a few circuit simulation results without the pre-knowledge of circuit device SPICE parameters. The expression is well suited to predict period PSIJ, ... » read more

How Memory Design Optimizes System Performance
By John Koon - 21 Sep, 2022 - Comments: 0

Exponential increases in data and demand for improved performance to process that data has spawned a variety of new approaches to processor design and packaging, but it also is driving big changes on the memory side. While the underlying technology still looks very familiar, the real shift is in the way those memories are connected to processing elements and various components within a syste... » read more

DDR Memory Test Challenges From DDR3 to DDR5
By Keysight - 21 Sep, 2022 - Comments: 0

Cloud, networking, enterprise, high-performance computing, big data, and artificial intelligence are propelling the development of double data rate (DDR) memory chip technology. Demand for lower power requirements, higher density for more memory storage, and faster transfer speeds are constant. Servers drive the demand for next-generation DDR. Consumers benefit when existing and legacy generati... » read more

Open-Short Normalization Method For A Quick Defect Identification In Branched Traces With High-Resolution Time-Domain Reflectometry
By Advantest - 07 Sep, 2022 - Comments: 0

Time-domain reflectometry (TDR) that employs electro-optical sampling affords excellent resolution at the femtosecond level and exhibits a comprehensible impulse waveform, thereby allowing quick defect identification in a single trace. However, it remains challenging to identify a defect in a trace of multiple branches; the TDR waveform is complex. Generally, the TDR waveform of a defective uni... » read more

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