Special Reports
Agentic AI Is Changing Data Center Architectures
Standalone GPUs are being replaced by heterogeneous SoCs and chiplets that combine CPUs, GPUs, and NPUs to eliminate memory bottlenecks, reduce latency, and boost efficiency.
Top Stories
Can AI Create Missing Models?
It depends on what those models are used, which also can have a big impact on the cost.
PCIe Benefits From AI, Despite Scaling Protocols
CXL is also gaining traction in AI processing, while MIPI and others are growing at the edge.
Video
1 Megawatt Racks In Data Centers
A look inside the next-generation AI server rack.
Sponsor Blogs
Siemens EDA’s Matt Grange digs into thermal and mechanical issues in 2.5D and 3D-IC designs, in Mastering 3D-IC Verification Complexity.
Rambus’ Carlos Weissenberg explains why tight coordination between clocking, power delivery, and system-level management is necessary at higher data rates, in Clocked DDR5 Client Memory Modules Enable Scaling To 9600 MT/s For AI PCs.
Expedera’s Sharad Chole examines packet-based architectures and how they can enable out-of-order execution to optimize hardware utilization without retraining the model, in How To Start Building Edge-Native AI.
Ayar Labs’ Nandita Aggarwal and Wiwynn’s Nicholas Chang discuss how co-packaged optics can deliver the bandwidth density and efficiency needed to scale AI compute clusters, in Building A Production-Ready Optically Connected Rack For AI Scale-Up.
Cadence’s Shyam Sharma explores a new architecture that enables higher data rates and densities while remaining pin-compatible with traditional DIMM, in DDR5 MRDIMM: A Transformational Evolution For DDR5 DIMM.
Synopsys’ Lakshmi Jain and Wei-Yu Ma look at a new approach for hybrid-bonded 3D integration, in Re-Architecting Die-To-Die IO For AI.
Arm’s Odin Shen shows how developers can turn model experimentation into concrete observation of edge AI workloads across different scenarios, in Beyond The Demo: Deploying And Evaluating Open-Source AI Workloads.
Sponsor White Papers
Building Edge AI with IP Solutions
Five architectural domains that are shaped by edge-deployment reality, and how priorities shift across the two primary deployment tiers: edge infrastructure and edge devices.
Foundation IP: Pushing the Boundaries of Energy-Efficient Chip Design
Energy-efficient SoC design, optimizing PPA, deep low-voltage operation, and advanced power management techniques.
Shift-left Schematic Memory Contention Analysis
Early intervention strategies for memory design bottlenecks and contention risks.
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