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A Primer On Last-Level Cache Memory For SoC Designs


System-on-chip (SoC) architects have a new memory technology, last level cache (LLC), to help overcome the design obstacles of bandwidth, latency and power consumption in megachips for advanced driver assistance systems (ADAS), machine learning, and data-center applications. LLC is a standalone memory that inserts cache between functional blocks and external memory to ease conflicting requireme... » read more

Artificial Intelligence Chips: Past, Present and Future


Artificial Intelligence (AI) is much in the news these days. AI is making medical diagnoses, synthesizing new chemicals, identifying the faces of criminals in a huge crowd, driving cars, and even creating new works of art. Sometimes it seems as if there is nothing that AI cannot do and that we will all soon be out of our jobs, watching the AIs do everything for us. To understand the origins ... » read more

Not Enough Respect For SoC Interconnect


For high-volume system-on-chip (SoC) applications—artificial intelligence (AI), automotive, mobility, solid state drives and more—effective interconnect technology can generate hundreds of millions of dollars in revenue due to smaller chip area, better functionality and faster delivery of SoC platforms. State-of-the-art interconnect technology also allows chip designers to create SoC deriva... » read more

Neural Nets In ADAS And Autonomous Driving SoC Designs


Automotive electronics has ushered in a new wave of semiconductor design innovation and one new technology gaining a lot of attention is neural networks (NNs). Advanced driving assistance systems (ADAS) and autonomous car designs now rely on NNs to meet the real-time requirements of complex object-recognition algorithms. The concept of NNs has been around since World War II, promising a futu... » read more

How SoC Interconnect Enables Flexible Architecture For ADAS And Autonomous Car Designs


When the mobile phone era saw its fastest growth, the design teams that were the most innovative were able to introduce game-changing features before anyone else. Those companies also had the most configurable interconnect IP, allowing them to adapt to quickly changing market needs faster than their competition. Now, nearly a decade later, when autonomous driving is quickly moving into the m... » read more

Building In Functional Safety At The Lowest Hardware Levels Supports Autonomous Driving’s Future


Long before automotive electronic system designers chose artificial intelligence and machine learning as the path toward the future of autonomous driving’s future, it was clear that high-performance computing platforms typically found in data center systems clearly were not going to provide all the answers. Automotive system designers place more emphasis on functional safety and resilience, w... » read more

Heterogeneous Cache Coherence Requires A Common Internal Protocol


Machine learning and artificial intelligence systems are driving the need for systems-on-chip containing tens or even hundreds of heterogeneous processing cores. As these systems expand in size and complexity, it becomes too difficult to manage data flow solely through software means. An approach that simplifies software while improving performance and power consumption is to implement hardware... » read more

ADAS Design Shifts Toward Hardware


Autonomous driving will challenge system-level designers like never before with the simultaneous integration of three critical areas: Supercomputing complexity, real-time embedded performance, and functional safety. To get there, developers will need to shift their focus from a software-centric approach toward custom hardware development to produce a system that meets the safety, cost, and powe... » read more

Avoiding Traffic Jams In SoC Design


While sitting in a traffic jam on the way to work, I realized that the sheer volume of vehicles on the road exceeds the capacity originally planned for by civil engineers, when highways first hit the drawing boards 50 or 60 years ago. It dawned on me that there is a parallel to today’s System-on-Chip design—engineers are struggling to close timing on the interconnect during the back-end pla... » read more

Reducing Latency In ADAS SoC Design Enhances QoS For Digital Mirroring


The state-of-the-art of Advanced Driver Assistance Systems (ADAS) is quickly changing, and ADAS chip engineers are finding that on-chip quality-of-service (QoS) is becoming a system-level constraint on ADAS performance. Designers need innovative approaches to address these issues, which is why Dream Chip Technologies highlighted one such method in a recent presentation. Dream Chip Technologi... » read more

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