Author's Latest Posts

A Game-Changer For IP Designers: Design-Stage Verification
By Siemens EDA - 28 Feb, 2024 - Comments: 0

Discover how to transform your IP design process with the Calibre Shift left initiative. In this new technical paper, you’ll gain valuable insights into how, by moving physical verification earlier in the IP design flow, you can locate and correct design errors sooner, reducing costs and getting complex designs to market faster. Dive into the challenges of hard, soft and custom IP creation, a... » read more

IC Package Physical Design Best Practices
By Siemens EDA - 15 Feb, 2024 - Comments: 0

Historically IC package design has been a relatively simple task which allowed the die bumps to be fanned out on a package substrate to a floorplan geometry suitable for connecting to a printed circuit board (PCB). But today the industry is moving to disaggregation of traditional monolithic SoC functions into chiplets often interfaced with local high-speed memory to avoid silicon reticle limits... » read more

Mastering Complexity Leveraging Digital Threads For Electronics Systems Design And Manufacturing
By Siemens EDA - 25 Jan, 2024 - Comments: 0

The rapid advancement of technology and its integration into various industries, particularly the electronics sector, has led to a significant increase in complexity. Digital threads offer a seamless framework for data flow throughout a product’s lifecycle, from ideation to utilization, fostering collaboration and informed decision-making. They intersect various domains, ensuring information ... » read more

Extending Design Technology Co-Optimization From Technology Launch To HVM With Calibre Fab Solutions
By Siemens EDA - 21 Dec, 2023 - Comments: 0

As IC designs get larger and manufacturing processes get more complex, the semiconductor industry finds itself needing new solutions to prevent the propagation of systematic defects, streamline product cycle time and deliver high-quality, reliable chips. Traditionally, engineers have improved performance, power efficiency, density and cost through design-technology co-optimization (DTCO) techni... » read more

Achieving High-Performance, Low-Power Design Optimization With The Solido Library IP Solution
By Siemens EDA - 13 Dec, 2023 - Comments: 0

Achieving overall power, performance, and area (PPA) targets is a key goal for today’s advanced IC design projects. To accomplish this, standard cell and memory libraries must be optimized for PPA. In this white paper, we describe how the Siemens Solido IP Library Solution helps engineering teams design and verify library IP to optimize PPA tradeoffs, maximize yield, and validate for easy int... » read more

Use Advanced DFT And Silicon Bring Up To Accelerate AI Chip Design
By Siemens EDA - 07 Dec, 2023 - Comments: 0

The market for AI chips is growing quickly, with the 2022 revenue of $20B expected to grow to over $300B by 2030. To keep up with the demand and stay competitive, AI chip designers set aggressive time-to-market goals. Design teams looking for ways to shave significant time off chip development time can look to advanced DFT and silicon bring up techniques described in this paper, including hiera... » read more

Successful 3D-IC Design, Verification, And Analysis Requires An Integrated Approach
By Siemens EDA - 30 Nov, 2023 - Comments: 0

3D-IC designs enable improvements in performance, power, footprint, and costs that cannot be attained in system-on-chip (SoC) and IC design. However, the leap from traditional SoC/IC design to 3D-IC designs brings not only new opportunities, but also new challenges. Siemens EDA provides multiple 3D-IC design analysis and verification functionalities that address the diverse needs of 3DIC des... » read more

Placement And CTS Techniques For High-Performance Computing Designs
By Siemens EDA - 09 Nov, 2023 - Comments: 0

This paper discusses the challenges of designing high-performance computing (HPC) integrated circuits (ICs) to achieve maximum performance. The design process for HPC ICs has become more complex with each new process technology, requiring new architectures and transistors. We highlight how the Siemens Aprisa digital implementation solution can solve placement and clock tree challenges in HPC de... » read more

Placement And CTS Techniques For High-Performance Computing Designs
By Siemens EDA - 09 Nov, 2023 - Comments: 0

This paper discusses the challenges of designing high-performance computing (HPC) integrated circuits (ICs) to achieve maximum performance. The design process for HPC ICs has become more complex with each new process technology, requiring new architectures and transistors. We highlight how the Siemens Aprisa digital implementation solution can solve placement and clock tree challenges in HPC de... » read more

Automotive Safety Island
By Siemens EDA - 02 Nov, 2023 - Comments: 0

The promise of autonomous vehicles is driving profound changes in the design and testing of automotive semiconductor parts. Automotive ICs, once deployed for simple functions like controlling windows, are now performing complex functions related to advanced driver-assist systems (ADAS) and autonomous driving applications. The processing power required results in very large and complex ICs that ... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2024 SMG   |  Terms of Service  |  Privacy Policy