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System-level Reliability Verification for 2.5D/3D ICs Using Innovator3D IC and Calibre 3DPERC
By Siemens EDA - 04 Mar, 2026 - Comments: 0

The increasing demand for higher performance, lower power, and greater functionality in smaller packages has driven the rapid adoption of 2.5D and 3D Integrated Circuits (ICs). However, the inherent complexity of these multi-die architectures presents significant reliability verification challenges that traditional 2D flows cannot adequately address, particularly concerning electrostatic discha... » read more

Accelerate Your IP Selection With Smart Solido Library Profiler
By Siemens EDA - 02 Mar, 2026 - Comments: 0

This white paper discusses the IP selection process, its requirements, challenges, and proposed solutions. The process of choosing cell IP libraries for integrated circuit (IC) design is a slow and complicated process due to the inconsistencies and complexities of library files, particularly across sources, technology nodes, and variants. Manual methods to achieve IP selection not only consumes... » read more

How Siemens Symphony Pro Enabled AnalogPort To Verify Complex Chip Interfaces
By Siemens EDA - 13 Feb, 2026 - Comments: 0

The semiconductor industry's shift toward chiplet-based architectures has created significant mixed-signal verification challenges for high-speed die-to-die interconnects. Traditional verification approaches force difficult trade-offs: Digital mixed-signal (DMS) flows sacrifice analog fidelity, while Analog mixed-signal (AMS) flows struggle with scalability and manual overhead. This paper detai... » read more

New Innovative Way to Functionally Verify Heterogeneous 2D/3D Package Connectivity
By Siemens EDA - 28 Jan, 2026 - Comments: 0

The heterogeneous integration of multiple chiplets in a single packaging platform is critical for many high performance compute segemnts such as AI, Hyperscalers, Cloud datacenters, Neural processors and even autonomous vehicles. With the quantity of chiplets commonly exceeding double-digit numbers. Add to that the increasing usage of high-speed, low power and low latency high-bandwidth-memory ... » read more

Formal Verification Of Synthesizable C++/SystemC Designs
By Siemens EDA - 07 Jan, 2026 - Comments: 0

Formally checking generated RTL can be difficult to analyze as errors cannot be correlated to the HLS source code. Questa HLV can help overcome this challenge with high-level verification. Siemens offers several apps to verify and clean C++ HLS code before running HLS and then check the equivalency between C++ and RTL. High-level synthesis (HLS) is a design flow in which design intent is des... » read more

The Power Of Shift-Left DRC Verification With Calibre nmDRC Recon
By Siemens EDA - 23 Dec, 2025 - Comments: 0

As integrated circuit (IC) designs grow in complexity, traditional design rule checking (DRC) methods struggle to keep pace. Originally developed for simpler, custom layouts, traditional DRC uses an iterative “construct by correction” method. However, with the rise of automation and multi-layered design hierarchies, relying on traditional sequential DRC approaches can create substantial run... » read more

Evaluating A PDN Based On Jitter
By Siemens EDA - 11 Dec, 2025 - Comments: 0

Power distribution networks (PDN) must supply current fast enough to meet the switching needs of high-performance integrated circuits. As the voltage regulator module can only supply current up to a limited frequency range, decoupling capacitors are added to the PDN to provide a low impedance path for current to flow to the IC. This paper describes a simulation methodology to automatically meas... » read more

Calibre 3DPERC: Your Key To Robust ESD Solutions For 3D ICs
By Siemens EDA - 03 Dec, 2025 - Comments: 0

As semiconductor designs move beyond the limits of planar integration, three-dimensional (3D) IC technology introduces new challenges for ESD (electrostatic discharge) protection and verification. In this paper, author Dina Medhat explores how traditional verification methods must evolve for 3D ICs, detailing the crucial differences in pad classification, protection circuit strategies and the i... » read more

Guarantee IP Integrity With Calibre IP Checker
By Siemens EDA - 25 Nov, 2025 - Comments: 0

In complex SoC designs, intellectual property (IP) blocks are critical yet vulnerable. Unintended modifications to IP during placement, routing or fill stages often go undetected by traditional DRC, leading to functional failures, performance degradation and costly re-spins. This paper introduces Calibre IP Checker, an automated, shift-left solution designed to guarantee IP integrity. It works ... » read more

Standardization Of HDMs For Hierarchical CDC And RDC Analysis
By Siemens EDA - 12 Nov, 2025 - Comments: 0

Currently hierarchical data models (HDM) must be generated with the same EDA tool that customers will use to consume the HDM for CDC and RDC analysis at the SoC level. To resolve this problem a CDC Working Group was created within the Accellera organization. The goal of this Working Group is to create a standard format for HDMs so the models can be consumed by any EDA tool irrespective of the s... » read more

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