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Standardization Of HDMs For Hierarchical CDC And RDC Analysis
By Siemens EDA - 11 Nov, 2025 - Comments: 0

Currently hierarchical data models (HDM) must be generated with the same EDA tool that customers will use to consume the HDM for CDC and RDC analysis at the SoC level. To resolve this problem a CDC Working Group was created within the Accellera organization. The goal of this Working Group is to create a standard format for HDMs so the models can be consumed by any EDA tool irrespective of the s... » read more

Combining SPICE With IBIS-AMI: Solving Advanced Signal Integrity Verification Challenges With Solido SPICE
By Siemens EDA - 06 Nov, 2025 - Comments: 0

This paper explores current technology trends in high-speed links, including high-speed memory and SerDes applications, highlighting the critical roles of combined SPICE-level and IBIS-AMI modeling for accurate verification. Verifying high-speed links with IBIS-AMI during the circuit design phase presents significant complexity due to the combined effects of equalization schemes, channel S-para... » read more

Smart Handling Of Reset Domain Crossings To Non-Resettable Flip-Flops
By Siemens EDA - 30 Oct, 2025 - Comments: 0

The importance of reset domain crossing (RDC) verification in ensuring robust and reliable SoC operation cannot be overstated. Verification tools for RDCs are essential in identifying potential metastability issues and ensuring that signal transitions across reset domains are properly handled. This paper presents a novel approach to tackling the challenges of RDC verification involving non-rese... » read more

Frequency-Impedence Verification Of Power Delivery Network With HyperLynx PI For AMD Versal Adaptive SoC Devices
By Siemens EDA - 15 Oct, 2025 - Comments: 0

HyperLynx Decoupling analysis and the PDN Decoupling Optimizer are powerful tools for exploring various PDN structures and decoupling strategies. This paper presents a study showcasing the advantages of performing a HyperLynx decoupling analysis to verify PDN performance, and it highlights the extensive collaboration between Siemens and AMD in creating a complete system design flow for performi... » read more

Raising The Bar In Mission-Critical Verification
By Siemens EDA - 09 Oct, 2025 - Comments: 0

The 2024 Siemens EDA and Wilson Research Group Functional Verification Study provides an in-depth analysis of current trends in FPGA design and verification, with a particular focus on the aerospace and defense (A&D) sector. The study highlights the increasing complexity of FPGA designs driven by factors such as embedded processors, asynchronous clock domains, and stringent security and saf... » read more

Preparing For The Multiphysics Future Of 3D-ICs
By Siemens EDA - 29 Sep, 2025 - Comments: 0

3D integrated circuits (3D ICs) are emerging as a revolutionary approach to design, manufacturing and packaging in the semiconductor industry. Offering significant advantages in size, performance, power efficiency and cost, 3D ICs are poised to transform the landscape of electronic devices. However, with 3D ICs come new design and verification challenges that must be addressed to ensure success... » read more

Verifying The Evolving UCIe Landscape
By Siemens EDA - 10 Sep, 2025 - Comments: 0

This paper details a verification strategy for UCIe 3.0 designs, integrating both legacy manageability architecture and emerging UCIe 3.0 features into a reusable, scalable framework. Built on a layered UVM architecture, Questa One Avery VIP for UCIe enables flexible modeling of complex domains through configurable APIs and supports automated discovery and routing table setup for both direct an... » read more

Calibre 3DStress: Advanced Stress Analysis For Reliable 3D IC Design
By Siemens EDA - 03 Sep, 2025 - Comments: 0

As the industry transitions toward advanced 3D IC architectures and heterogeneous integration, managing thermo-mechanical stress is essential for product quality and long-term reliability. Calibre 3DStress enables design and packaging teams to simulate, analyze and disposition stresses imparted on the chip during or after the packaging process, ensuring that potential failure risks—such as wa... » read more

Launching The Full Potential Of 3D IC With Front-End Architectural Planning
By Siemens EDA - 19 Aug, 2025 - Comments: 0

3D IC and chiplet-based design have the potential to accelerate the pace of semiconductor industry innovation. 3D IC design teams pack more functionality closer together and achieve higher levels of systems integration and performance in a smaller footprint faster than what’s possible with traditional SoC implementation. To achieve the full potential of 3D IC, teams need cost-effective fro... » read more

FuSa Flow For Achieving An ASIL-C Safety Architecture
By Siemens EDA - 07 Aug, 2025 - Comments: 0

ISO 26262, titled “Road vehicles – Functional safety,” is an international standard for the functional safety of electrical and electronic systems in road vehicles. First published in 2011 and revised in 2018, ISO 26262 adapts the broader IEC 61508 standard for automotive applications. The ISO 26262 standard underscores the importance of achieving specific random hardware failure rate tar... » read more

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