Agentic AI Is Changing Data Center Architectures

By Ann Mutschler - 11 Jun, 2026 - Comments: 0

Key Takeaways: The rise of agentic AI is shifting data centers from GPU-centric number crunching to CPU-driven orchestration, where managing long-running reasoning loops and context is just as important as raw compute. Integrating CPUs, GPUs, and stacked memory into tightly coupled multi-die architectures with varying workloads makes it much harder to ensure they will be reliable and ef... » read more

Can AI Create Missing Models?

By Brian Bailey - 11 Jun, 2026 - Comments: 0

Key takeaways Models are an essential part of EDA flows, each capturing necessary detail while retaining good execution performance. Models have been expensive to create, maintain and verify, restricting their utilization, but AI may be able to significantly reduce their cost. A deeper question remains. Should AI be used to create models that help existing flows, or should AI be used... » read more

Mastering 3D-IC Verification Complexity

By Matt Grange - 11 Jun, 2026 - Comments: 0

The semiconductor industry's transition from traditional 2D integrated circuits to 2.5D and 3D-IC configurations represents more than an incremental advancement. This architectural shift, driven by the need to push beyond conventional scaling limitations, introduces a cascade of verification challenges that legacy methodologies struggle to address. As designs incorporate multiple stacked dies, ... » read more

Why Analog And Mixed-Signal Chips Resist Adaptive Test

By Gregory Haley - 09 Jun, 2026 - Comments: 0

Key Takeaways Analog and mixed-signal test remains heavily specification-based because the measurements do not always produce a single expected result. The absence of objective coverage metrics has historically encouraged conservative test flows, which IEEE 2427-2025 begins to address. Separating device behavior from test-path variation is a prerequisite for any adaptive flow—and h... » read more

Test Anything, Anywhere, Anytime

By Peter Orlando - 09 Jun, 2026 - Comments: 0

The semiconductor industry is under relentless pressure to deliver devices that are not only high-performing but also exceptionally reliable across their entire lifecycle. From the moment a chip is tested at the wafer to its deployment in complex systems such as data centers and automotive platforms, the expectation is clear: zero-defect quality at shipment and continuous reliability in the fie... » read more

Reduce Memory Redesigns With Shift-Left

By Chun-hsiang Chang - 05 Jun, 2026 - Comments: 0

Engineering managers overseeing memory design know the pattern well: a promising architecture moves smoothly through schematic capture and into layout, only to stumble when integration testing reveals contention issues that force expensive redesigns. Address decoders that looked correct in isolation turn out to enable multiple banks simultaneously. Power switches configured for aggressive gatin... » read more

A Comprehensive Approach To 3D-IC Physical Verification

By Siemens EDA - 05 Jun, 2026 - Comments: 0

3D integrated circuits (3D ICs) are reshaping semiconductor development. While these architectures deliver significant performance, power and integration gains, they introduce new challenges in verification—across electrical, thermal and mechanical domains. Siemens Calibre offers a comprehensive platform for 3D IC physical verification, linking DRC, LVS, advanced thermal simulation, mechanica... » read more

Blog Review: Jun. 3

By Jesse Allen - 03 Jun, 2026 - Comments: 0

Siemens' Gordon Allan contends that verification IP gives design teams a practical way to verify standards-based interfaces and memories without rebuilding the same infrastructure generation after generation and shares key evaluation metrics. Synopsys' Sutirtha Kabir suggests that successful multi-die design will require deeper collaboration from early architecture exploration to manufacturi... » read more

Toward Agentic Verification

By Brian Bailey - 28 May, 2026 - Comments: 1

Key Takeaways: Agentic verification provides flow orchestration for common repetitive tasks. Capabilities will expand when tools can learn from a larger context, including the specification. Design houses need to fully understand the costs and benefits and plan accordingly. Agentic verification is more than a buzzword. It is a pivotal moment in the evolution of verification ... » read more

Observability Is Essential For Modern Silicon

By Ann Mutschler - 28 May, 2026 - Comments: 0

Experts At The Table: In-silicon observability — also known as on-die or on-chip visibility — is becoming increasingly important for managing the performance, reliability, and security of today’s high-performance systems. Semiconductor Engineering sat down to discuss this with Andy Nightingale, vice president of product management and marketing at Arteris; Nandan Nayampally, chief commerc... » read more

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