Self-Heating Issues Spread


With every new node there are additional physical effects that must be considered, but not all of them are of the same level of criticality. One that is being mentioned more frequently is self-heating. All devices consume power and when they do that, it becomes heat. "In essence, all active devices generate heat as carriers move, creating channels for current to pass through the gates," says... » read more

Week In Review: Design, Low Power


Arm is expected to list solely on a U.S. stock exchange when it goes public again later this year, forgoing the London Stock Exchange for now, the BBC reports. Global investment banks expect the offering to value the company between $30 billion and $70 billion, according to Bloomberg. Disaggregating chips into specialized processors, memories, and architectures is becoming necessary for cont... » read more

100G Ethernet IP For Edge Computing


The presence of Ethernet in our lives has paved the way for the emergence of the Internet of Things (IoT). Ethernet has connected everything around us and beyond, from smart homes and businesses, to industries, schools, and governments. This specification is even found in our vehicles, facilitating communication between internal devices. Ethernet has enabled high-performance computing data cent... » read more

Uneven Circuit Aging Becoming A Bigger Problem


Circuit aging is emerging as a first-order design challenge as engineering teams look for new ways to improve reliability and ensure the functionality of chips throughout their expected lifetimes. The need for reliability is obvious in data centers and automobiles, where a chip failure could result in downtime or injury. It also is increasingly important in mobile and consumer electronics, w... » read more

Blog Review: March 8


Synopsys' Rahul Thukral and Bhavana Chaurasia find that embedded MRAM is undergoing an uplift in utilization for low-power, advanced-node SoCs thanks to its high capacity, high density, and ability to scale to lower geometries. Siemens EDA's Chris Spear dives into the UVM Factory with a look at the  SystemVerilog Object-Oriented Programming concepts behind the factory. Cadence's Veena Pa... » read more

How Low Can You Go? Pushing The Limits Of Transistors


Deep low voltage enablement of embedded memories and logic libraries to achieve extreme low power: Rising demand for cutting-edge mobile, IoT, and wearable devices, along with high compute demands for AI and 5G/6G communications, has driven the need for lower power systems-on-chip (SoCs). This is not only a concern for a device’s power consumption when active (dynamic power), but also when... » read more

Test Challenges Mount As Demands For Reliability Increase


An emphasis of improving semiconductor quality is beginning to spread well beyond just data centers and automotive applications, where ICs play a role in mission- and safety-critical applications. But this focus on improved reliability is ratcheting up pressure throughout the test community, from lab to fab and into the field, in products where transistor density continues to grow — and wh... » read more

Compiler Optimization Made Easy


In a previous blog post, we discussed the benefits of using automation to maximize the performance of a system. One use case I mentioned was compiler flag mining, and the fact that performance is available beyond the standard optimization flags provided by most compilers. Getting to this untapped performance is a difficult problem to solve, but fortunately there is an easy way. A universe of o... » read more

How The Doubling Of Interconnect Bandwidth With PCI Express 6.0 Impacts IP Electrical Validation


As a result of the innovations taking place in CPUs, GPUs, accelerators, and switches, the interface in hyperscale datacenters now requires faster data transfers both between compute and memory and onto the network. PCI Express (PCIe®) provides the backbone for these interconnects and is used to build protocols such as Computer Express Link (CXL™) and Universal Chiplet Interconnec... » read more

Week In Review: Design, Low Power


Apple plans to spend an additional €1 billion (~$1.1B) over the next six years to expand its Munich, Germany-based Silicon Design Centre, including the construction of a new research facility. "The expansion of our European Silicon Design Centre will enable an even closer collaboration between our more than 2,000 engineers in Bavaria working on breakthrough innovations, including custom sil... » read more

← Older posts Newer posts →