Chip Industry Week In Review


By Jesse Allen, Gregory Haley, and Liz Allan. The Japanese government approved $3.9 billion in funding for chipmaker Rapidus to expand its foundry business, of which 10% will be invested in advanced packaging. This is in addition to the previously announced $2.18 billion in funding. In a meeting next week, the U.S. and Japan are expected to cooperate on increasing semiconductor development a... » read more

Integrating ADAS/IVI SoCs Using Automotive IP


The automotive industry continues to evolve the centralized electrical/electronic (EE) architecture, impacting automakers, and Tier 1 and Tier 2 suppliers, as they implement various applications over the next 10 years. The new architecture is structured around a centralized compute module which executes multiple applications such as Advanced Driver Assistance Systems (ADAS)/highly automated dri... » read more

Quantum Computing Challenged By Security, Error Correction


The number and volume of warnings about a post-quantum cryptography (PQC) world are rising, as governments, banks, and other entities prepare for a rash of compromised data and untrustworthy digital signatures. Exactly when this will become a genuine threat is still somewhat fuzzy, because it depends on progress in developing robust qubits. A report by McKinsey & Co. estimates that by 20... » read more

Data Center Security Issues Widen


The total amount of data will swell to about 200 zettabytes of data next year, much of it stored in massive data centers scattered across the globe that are increasingly vulnerable to attacks of all sorts. The stakes for securing data have been rising steadily as the value of that data increases, making it far more attractive to hackers. This is evident in the scope of the attack targets —... » read more

AI Takes Aim At Chip Industry Workforce Training


When all the planned fabs become operational, the semiconductor industry is likely to face a worker shortage of 100,000 each in the U.S. and Europe, and more than 200,000 in Asia-Pacific, according to a McKinsey report. Since the dawn of technology, people have worried that robots, automation, and AI will steal their jobs, but these tools also can be put to use to help fill the chip industry ta... » read more

Blog Review: Apr. 3


Siemens' Keith Felton finds that high bandwidth memory integration poses significant challenges for package designers stemming from its unique architecture and stringent performance requirements. Synopsys' Gervais Fong finds out what's new in the USB4 v2 specification, some of its unique challenges involved in doubling the performance capabilities of the USB wired connection, and an intrigui... » read more

Faster And Better Floorplanning With ML-Based Macro Placement


The chips contained in today’s consumer and commercial electronic products are staggering in size and complexity. The largest devices include central processing units (CPUs), graphics processing units (GPUs), and system-on-chip (SoC) devices that integrate many functions on a single die. Additionally, chips are expanding beyond their traditional borders with multi-die approaches such as 2.5DI... » read more

The Challenges Of Working With Photonics


Experts at the Table: Semiconductor Engineering sat down to talk about where photonics is most useful — and most vulnerable — with James Pond, fellow at Ansys; Gilles Lamant, distinguished engineer at Cadence; and Mitch Heins, business development manager for photonic solutions at Synopsys. What follows are excerpts of that conversation. To view part one of this discussion, click here. ... » read more

What’s Missing In 2.5D EDA Tools


Gaps in EDA tool chains for 2.5D designs are limiting the adoption of this advanced packaging approach, which so far has been largely confined to high-performance computing. But as the rest of the chip industry begins migrating toward advanced packaging and chiplets, the EDA industry is starting to change direction. There are learning periods with all new technologies, and 2.5D advanced pack... » read more

Interconnects Essential To Heterogeneous Integration


Designing and manufacturing interconnects is becoming more complex, and more critical to device reliability, as the chip industry shifts from monolithic planar dies to collections of chips and chiplets in a package. What was once as simple as laying down a copper trace has evolved into tens of thousands of microbumps, hybrid bonds, through-silicon vias (TSVs), and even junctions for optical ... » read more

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