Technical Paper Home

Design & Verification

• Field-Coupled Nanocomputing: Scalable And Efficient Post-Layout Optimization (TU Munich)

  Published on March 7, 2025

• Solution To Read Disturbance For Current And Future DRAM Chips at Low Area, Performance And Energy Costs (ETH Zurich et al.)

  Published on March 7, 2025

• Understanding Fault Injection Attacks At The Pre-Silicon Level

  Published on March 7, 2025

• RISC-V High Performance Multicore and GPU SoC Platform For Safety Critical System

  Published on March 3, 2025

• 3D Stacked Device Architecture Enabled By BEOL-Compatible Transistors (Stanford et al.)

  Published on February 26, 2025

• SW-HW Co-Design Mitigation To Strengthen ASLR Against Microarchitectural Attacks (MIT)

  Published on February 26, 2025

• Design Space For The Device-Circuit Codesign Of NVM-Based CIM Accelerators (TSMC)

  Published on February 24, 2025

• Cradle-To-Grave Analysis Of The Carbon Footprint of AI Hardware (Google)

  Published on February 24, 2025

• HW-Aligned Sparse Attention Architecture For Efficient Long-Context Modeling (DeepSeek et al.)

  Published on February 18, 2025

• Modeling and Simulation of NVM Technologies: Tutorial (TU Dormand, TU Dresden, KIT, FAU)

  Published on February 17, 2025
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