Technical Paper Home

Design & Verification

• Reverse Engineering Approach for Evaluating HW IP Protection ( U. of Florida, Indiana U.)

  Published on January 23, 2025

• Parallelized Compilation Pipeline Optimized for Chiplet-Based Quantum Computers

  Published on January 21, 2025

• Design-Space Analysis of M3D FPGA With BEOL Configuration Memories (Georgia Tech, UCLA)

  Published on January 17, 2025

• Design Space for the Device-Circuit Codesign of NVM-Based CIM Accelerators (TSMC)

  Published on January 15, 2025

• Geometric-Aware Model Merging Approach To Enhance Instruction Alignment in Chip LLMs (Nvidia)

  Published on January 15, 2025

• Schottky Barrier Transistors: Status, Challenges and Modeling Tools

  Published on January 8, 2025

• Designing Heterogeneous AI Acceleration SoCs

  Published on January 6, 2025

• In-Depth Study of Low-Power MCUs For Wearables (EPFL)

  Published on December 28, 2024

• 98 Hardware Security Failure Scenarios (NIST)

  Published on December 3, 2024

• The Vulnerability of Clock Trees to Asymmetric Aging

  Published on December 3, 2024
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