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Technical Paper Home

Design & Verification

  • Lower Energy, High Performance LLM on FPGA Without Matrix Multiplication

    Published on June 27, 2024
  • Overview of Test Strategies for 3DICs

    Published on June 26, 2024
  • Thermoelectric Active Cooling Hot Spots in Chips

    Published on June 26, 2024
  • Using Formal Verification To Evaluate The HW Reliability Of A RISC-V Ibex Core In The Presence Of Soft Errors

    Published on May 31, 2024
  • Competitive Open-Source EDA Tools

    Published on May 19, 2024
  • Leveraging LLMs To Explain EDA Synthesis Errors And Help Train New Engineers 

    Published on May 8, 2024
  • Thermal Crosstalk Modelling And Compensation Methods for Programmable Photonic ICs (TU Denmark, iPronics)

    Published on May 7, 2024
  • A Design And Benchmarking Study Of CAM At 7nm In The Context Of Similarity Search Applications (Georgia Tech)

    Published on May 7, 2024
  • Distributing RTL Simulation Across Thousands Of Cores On 4 IPU Sockets (EPFL)

    Published on May 2, 2024
  • Merging Power and Arithmetic Optimization Via Datapath Rewriting (Intel, Imperial College London)

    Published on April 19, 2024
    • Page 12 of 34
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