Technical Paper Home

Design & Verification

• AUTOSAR-Aligned Analysis Of 180 SoC Vulnerabilities In Auto Architecture (Chalmers, Univ. of Gothenburg)

  Published on October 29, 2025

• Multimodal LLM Assistant for Chip Physical Design (National Taiwan Univ., UCLA, NVIDIA)

  Published on October 28, 2025

• Thermal Simulation And Optimization in 3D-IC Design (Intel, UCSB, Cadence)

  Published on October 22, 2025

• 3D Stacked HBM and Accelerators for LLMs: Heat Management and PDN (Georgia Tech, SK Hynix)

  Published on October 17, 2025

• Beyond BPD: Backside Clock and Signal Routing for Sub-3nm (UT Austin, Intel)

  Published on October 17, 2025

• Microelectronics and Advanced Packaging Technologies Roadmap 2.0 (SRC)

  Published on October 14, 2025

• Heterogeneous System With Specialized HW For Disaggregated LLM Inference (Princeton Univ., Univ. of Washington)

  Published on October 14, 2025

• LLM-Based AI Agent That Automates The Transistor Sizing Process (Univ. of Edinburgh)

  Published on October 10, 2025

• Framework for Optimizing Reliability and Thermal Management of 3DICs (National Taiwan Univ., Lamar Univ.)

  Published on October 10, 2025

• AI-Empowered Analog IC Sizing Methods (Univ. of Glasgow Et Al.)

  Published on October 10, 2025
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