Technical Paper Home

Design & Verification

• 3D IC Partitioning and Placement Method That Optimizes For Critical Paths (POSTECH)

  Published on September 12, 2024

• Hardware-Side-Channel Leakage Contracts That Account For Glitches and Transitions (TU Graz)

  Published on September 10, 2024

• GPU Microarchitecture Integrating Dedicated Matrix Units At The Cluster Level (UC Berkeley)

  Published on August 27, 2024

• LLMs In The High-Level Synthesis Design Flow

  Published on August 27, 2024

• 5 Novel Layout Design Methodologies For The 3nm Nanosheet FET Library (Samsung, KNU)

  Published on August 13, 2024

• A Hybrid ECO Detailed Placement Flow for Mitigating Dynamic IR Drop (UC San Diego)

  Published on August 1, 2024

• Using Diffusion Models to Generate Chip Placements (UC Berkeley)

  Published on July 27, 2024

• Formal Verification of Security Properties On RTL Designs

  Published on July 27, 2024

• NVMs: In-Memory Fine-Grained Integrity Verification Technique (Intel Labs, IISc)

  Published on July 16, 2024

• RTL Optimization Via Verified E-Graph Rewriting (Intel, Imperial College London)

  Published on July 8, 2024
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