Technical Paper Home

Packaging

• Defect Analysis and Testing Framework For FOWLP Interconnects

  Published on March 24, 2025

• EFO Errors In The Wire-Bonding Semiconductor Packaging Process

  Published on March 19, 2025

• Multi-Party Computation for Securing Chiplets

  Published on March 12, 2025

• A Novel Tier Partitioning Method in 3DIC Placement Optimizing PPA

  Published on March 11, 2025

• Thermal-Aware DSE Framework for 3DICs, With Advanced Cooling Models

  Published on March 11, 2025

• Thermally Aware Chiplet Placement Algorithm Based on Automatic Differentiation (MIT, IBM)

  Published on March 7, 2025

• 3D Stacked Device Architecture Enabled By BEOL-Compatible Transistors (Stanford et al.)

  Published on February 26, 2025

• FOWLP Warpage: Review Of Causes, Modeling And Methodologies For Controlling

  Published on February 14, 2025

• Potential of Wireless Interconnects For Improving Performance And Flexibility Of Multi-Chip AI Accelerators

  Published on February 7, 2025

• Optimization of the Inter-Chiplet Interconnect And The Chiplet Placement (ETH Zurich, U. of Bologna)

  Published on February 4, 2025
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