An new technical paper titled “Fast and Accurate Jitter Modeling for Statistical BER Analysis for Chiplet Interconnect and Beyond” was published by researchers at TSMC.
Abstract
“In this paper, we investigate Statistical Bit Error Rate (BER) analysis for low-loss short-reach chiplet interface and high-loss long-reach serial interface. We used jitter filtering to account for the residue jitter not tracked by a forwarded clock system and proposed a fast and exact Statistical BER method to account for the Tx jitter amplification effect in a high-loss channel. Our proposed method achieves a linear computation complexity.”
Find the technical paper here. July 2025.
S. Li and M. Amer, “Fast and Accurate Jitter Modeling for Statistical BER Analysis for Chiplet Interconnect and Beyond,” in IEEE Journal on Emerging and Selected Topics in Circuits and Systems, doi: 10.1109/JETCAS.2025.3592902.
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