tag: bit error rate

Pathfinding Method That Models ECC Overhead for Chiplet Interconnects (UCLA)
By Technical Paper Link - 16 Mar, 2026 - Comments: 0

A new technical paper, "Link Quality Aware Pathfinding for Chiplet Interconnects," was published by researchers at UCLA. Abstract "As chiplet-based integration advances, designers must select among short-reach die-to-die interconnect technologies with widely varying shoreline and areal bandwidth density, energy per bit, reach, and raw bit error rate (BER). Meeting stringent delivered BER ... » read more

Programmable Hardware Delivers 10,000X Improvement In Verification Speed Over Software For Forward Error Correction
By Tony Chan Carusone - 28 Aug, 2025 - Comments: 0

In the race to increase the speeds of wireline networking and communications, forward error correction (FEC) has become a vital part of the toolkit. To function effectively, especially with the increasing use of four-level pulse amplitude modulation (PAM4), high-speed protocols need FEC to avoid a rise in the number of reception errors. Each incremental increase in the transmitted symbol rate r... » read more

Statistical BER Analysis For Two Types Of Communication Systems In Chiplet Integration (TSMC)
By Technical Paper Link - 01 Aug, 2025 - Comments: 0

An new technical paper titled "Fast and Accurate Jitter Modeling for Statistical BER Analysis for Chiplet Interconnect and Beyond" was published by researchers at TSMC. Abstract "In this paper, we investigate Statistical Bit Error Rate (BER) analysis for low-loss short-reach chiplet interface and high-loss long-reach serial interface. We used jitter filtering to account for the residue jitt... » read more

224Gbps PHY For The Next Generation Of High Performance Computing
By Priyank Shukla - 18 Jul, 2024 - Comments: 0

Large language models (LLMs) are experiencing an explosive growth in parameter count. Training these ever-larger models requires multiple accelerators to work together, and the bandwidth between these accelerators directly limits the size of trainable LLMs in High Performance Computing (HPC) environments. The correlation between the LLM size and data rates of interconnect technology herald a... » read more

Overcoming Signal Integrity Challenges Of 112G Connections
By Cadence - 13 Mar, 2024 - Comments: 0

One of the big challenges with 112G SerDes (and, to a lesser extent, all SerDes) is handling signal integrity issues. In the worst case of a long-reach application, the signal starts at the transmitter on one chip, goes from the chip to the package, across a trace on a printed-circuit board (PCB), through a connector, then a cable or backplane, another connector, another PCB trace, another pack... » read more

The Quantum IoE
By Ernest Worthman - 08 Oct, 2015 - Comments: 0

The principle of quantum communication (QC) is that it can transfer a quantum state between locations. The significance of that cannot be overstated. This is what we can look to for the delivery of the super-secure communications networks of the future. This kind of secure communications is made to order for the IoE (and, of course, many other platforms). No matter how simple or complex the ... » read more

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