category: Top Stories

category: Auto, Security & Edge AI

Multi-die Testing In The Field Must Build On Established Test Methodologies
By Laura Peters - 07 Jul, 2026 - Comments: 0

Key Takeaways:  In-system testing is the very best way to ensure the longevity of data center and automotive hardware.  A 2-die monitor, test, and repair strategy requires a modified test strategy and new physical-aware bump repair.  Microbumps are too small to probe directly, so sacrificial pads enable probing.  The AI revolution is significantly outpacing the IC indust... » read more

Inspection And Metrology Catching Up For High-Density Fan-Out Panel Packaging
By Anne Meixner - 07 Jul, 2026 - Comments: 0

Key Takeaways:  To support AI/HPC devices, high-density fan-out on panels must deliver increased RDL layer count and micropillar height while decreasing the trace and bump/micropillar pitch.   Metrology and inspection steps assist with achieving known-good panel requirements to avoid throwing away expensive chiplets, such as HBM and TPUs.  Optical measurement systems need to acco... » read more

AI Models Transform Defect Inspection And Review, But Can Fail To Scale
By Laura Peters - 09 Jun, 2026 - Comments: 0

Key Takeaways: AI plays a role in improving defect capture rate and distinguishing between yield-killing and nuisance defects. New developments in wafer edge inspection are proving essential to bonded wafer yields. 70% of AI initiatives stall after pilot implementation, but some pitfalls can be avoided. One of the brightest spots in AI use today is the industry’s ability t... » read more

Why Analog And Mixed-Signal Chips Resist Adaptive Test
By Gregory Haley - 09 Jun, 2026 - Comments: 0

Key Takeaways Analog and mixed-signal test remains heavily specification-based because the measurements do not always produce a single expected result. The absence of objective coverage metrics has historically encouraged conservative test flows, which IEEE 2427-2025 begins to address. Separating device behavior from test-path variation is a prerequisite for any adaptive flow—and h... » read more

Co-Packaged Optics Testing Faces Steep Data Center Ramp
By Anne Meixner - 09 Jun, 2026 - Comments: 0

Key Takeaways: Device interface board must balance flexibility in handling with customization for different optical connectors. Test fixtures should account for DUT socketing challenges, such as warpage, coupling, and interference. Advanced data management practices will help speed yield learning. Integrating photonic and electrical ICs into co-packaged optics (CPO) requires... » read more

AI Accelerator Testing Depends On DFT Innovations
By Laura Peters - 12 May, 2026 - Comments: 0

Key Takeaways: I/O and lane repair capabilities are becoming critical to improving yield. System-level testing catches marginal defects and rare defects such as silent data corruption errors. Synopsys and TSMC developed a multi-die demo vehicle capable of full test, monitor, debug, and repair capability across the system’s lifecycle. The proliferation of accelerators in AI... » read more

Smart Test Collides With The Data Chain
By Gregory Haley - 12 May, 2026 - Comments: 0

Key Takeaways: The promise of smart test is a data-chain problem before it is an algorithm problem. A device can pass every checkpoint and still carry a latent defect the test record never captured. As test grows more adaptive, the validity of the measurement environment matters as much as the measurement itself. For years, the test roadmap has pointed toward more adaptive f... » read more

HBM Shifts Testing Left To Preserve AI Chip Yield
By Anne Meixner - 12 May, 2026 - Comments: 1

Key Takeaways: A high-yield, known-good stack requires multiple test insertions. Known good stack testing poses challenges for power delivery and thermal management. The shift to HBM4 and HBM5 will increase the pressure for shift-left test flows. Taller high-bandwidth memory (HBM) stacks and tighter TSV pitch are impacting AI module yields. The solution is to push test furth... » read more

What’s Failing At The Interface
By Gregory Haley - 07 Apr, 2026 - Comments: 0

Key Takeaways The interface is where failures in advanced packaging become visible, but it's increasingly not where they originate. Weak interfaces often don't fail at time zero, but they do degrade due to parametric drift and margin erosion that binary test screens miss entirely. The temporary test interconnect is the largest variable in the measurement chain and must be controlled ... » read more

AI Accelerators Usher In New Era For IC Test
By Laura Peters - 07 Apr, 2026 - Comments: 0

Key Takeaways The parallelism in AI accelerators enables low latency but complicates failure isolation. HBM can account for 50% of package cost, so known-good stack assurance is critical. DFT and test cooperate to solve final test, singulated die test, SLT, and in-system test for data centers. AI accelerators are used for everything from training large language models to mak... » read more

← Older posts

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2026 SMG   |  Terms of Service  |  Privacy Policy