Tool Matching Getting Tougher Across Test & Metrology


Key Takeaways Engineers leverage both device-specific and tool-level data to identify a process "sweet spot." Tight, frequent tool-to-tool matching enables greater yield and fab flexibility. Machine learning helps capture the nuances of a tool's signature. Many people outside of the semiconductor industry wonder how humans can fabricate transistors with tens of nanometer sca... » read more

Digital Twins: The Cloud’s The Limit


Key Takeaways Digital twins are gaining traction as a way of testing different options at every step of the design-through-manufacturing flow. AI can be used to glue together disparate data types in multi-physics simulations. The promise of digital twins is huge, but multiple challenges need to be solved before it can live up to its potential. Digital twin technology is draw... » read more

Catching Critical Defects In TSVs And Stacked Chips


Key Takeaways Variation is becoming a bigger problem in multi-die assemblies with TSVs and hybrid bonding. Multi-modal approaches are required to test these devices. AI plays a role in improving defect capture rate and distinguishing between yield-killing and false positives. New methods for interconnecting devices using through-silicon vias (TSVs) and hybrid bonding in stac... » read more

Resistance In Advanced Packages Is Now A System-Level Problem


Key Takeaways Kelvin measurement, which has been in use for decades, is no longer sufficient for addressing resistance in complex chips. The problem is that resistance is no longer concentrated in transistors, and where it does show up isn't always consistent or obvious. Traditional pass/fail approaches need to be replaced by more granular and flexible analytics and methodologies. ... » read more

Chiplets Add More Inspection And Test Steps


Key Takeaways Ensuring the reliability of multi-die assemblies requires a variety of approaches to detect subsurface defects. Bonds and interconnects are especially problematic and require more inspection insertions. Ensuring reliability requires connecting fragmented data that is often siloed. The shift to multi-die assemblies is forcing changes in how chips are tested and ... » read more

Wafer Probe Struggles To Adapt To Multi-Die Assemblies


Wafer probe, one of the key processes for ensuring reliability in semiconductor manufacturing, is becoming increasingly unreliable in multi-die assemblies and at leading-edge nodes. For much of the semiconductor industry’s history, wafer probe occupied a stable, largely uncontested role in manufacturing. It was understood as a screening step, an electrical checkpoint to identify failing de... » read more

Secure Data Sharing Becoming Critical For Chip Manufacturing


Semiconductor companies increasingly need to share data to solve problems faster, boost yield, and trace the root cause of failed devices. But to make that work, companies need assurances that their data will be secure, free from data leaks that could result in the loss of valuable IP. Data sharing is becoming critical at leading device nodes, where process variability is starting to consume... » read more

HBM4 Sticks With Microbumps, Postponing Hybrid Bonding


The next generation of high-bandwidth memory, HBM4, was widely expected to require hybrid bonding to unlock a 16-high memory stack. A JEDEC move made that unnecessary with this generation, but it’s merely a postponement, not a cancellation. HBM has been in high demand for AI in data centers — especially for training. Data movement dominates energy consumption, and high-bandwidth memories... » read more

Adaptive Test Gaining Ground For HPC And AI Chips


Adaptive test is starting to gain traction for high-performance computing and AI chips as test programs that rely on static limits and fixed test sequences reach their practical limits. The growing complexity of multi-die assemblies and power delivery, along with increased stresses, are forcing a shift toward real-time, data-driven optimization at the test cell. “It’s the same old pro... » read more

Metrology Digs Deep To Produce Next-Generation 3D NAND


Each generation of 3D NAND packs about 30% more bits than the previous version, with current devices storing up to 2 terabits of data in a die the size of a fingernail. With new product introductions shrinking from 18 months to every 12 months, chipmakers are constantly innovating to enable this prodigious scaling pace. 3D NAND technology is a core ingredient in mobile phones, solid-state dr... » read more

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