category: Test For The Autonomous Age

category: Auto, Security & Edge AI

Test Anything, Anywhere, Anytime
By Peter Orlando - 09 Jun, 2026 - Comments: 0

The semiconductor industry is under relentless pressure to deliver devices that are not only high-performing but also exceptionally reliable across their entire lifecycle. From the moment a chip is tested at the wafer to its deployment in complex systems such as data centers and automotive platforms, the expectation is clear: zero-defect quality at shipment and continuous reliability in the fie... » read more

Debugging Modern SoCs With Embedded Analytics: Instrumentation, Trace, And Faster Root-Cause Isolation
By Mike Sharp - 12 May, 2026 - Comments: 0

As SoCs chase ever higher performance and power efficiency, their designs have become harder to rootcause and harder to debug. Today’s devices combine billions of transistors with heterogeneous compute blocks and a growing mix of third‑party IPs, so failures can come from anywhere: a corner-case interaction between cores, an integration mistake, a timing assumption that no longer holds, or ... » read more

Analog Scan: Unlocking A New Era In Mixed-Signal Test
By Vladimir Zivkovic - 10 Mar, 2026 - Comments: 0

Anyone involved in IC product sign-off that includes a mixed signal design portion knows that developing robust tests for these intricate designs has historically been a significant bottleneck, no matter the application. It's a hurdle many of us have faced, leading to extended development times, high costs, and sometimes an unsettling uncertainty about the true quality of our tests. Traditio... » read more

Are You Using Structural Patterns In An SLT Environment?
By Peter Orlando - 10 Feb, 2026 - Comments: 0

Extending the in‑field life of your silicon is essential for long‑term success and for staying ahead of your competitors in today’s rapidly evolving digital world of data centers, automotive and cellular chipsets, and AI applications. For those reasons, it’s increasingly important to test your silicon in a System Level Test (SLT) environment. Testing in an SLT environment offers many be... » read more

Why Scan Diagnosis Should Be Part Of Every Fabless Company’s Yield Playbook
By Jayant D'Souza - 13 Jan, 2026 - Comments: 0

A fabless semiconductor company's world spins around two things, pushing design differentiation and getting those designs to market quickly and profitably. Yield isn’t just a manufacturing KPI. It's a business lever. And one of the most under-used levers in modern fabs is scan diagnosis, the practice of turning deterministic test infrastructure and failing test data into precise and action... » read more

Beyond The Core: Tackling System-Wide Debugging For Complex SoCs
By Francisca Tan - 09 Dec, 2025 - Comments: 0

The world of System-on-Chips (SoCs) is evolving – with the advancement of generative AI, the increasing demand for high-performance compute, and the innovative shift towards multi-chiplet architectures, system complexity is advancing at an increased pace. And with complexity comes an even greater challenge: debugging complexity. Silent data corruption, elusive timing-sensitive bugs, and i... » read more

Keeping The Lights On: How Digital Twins And Smart Semiconductor Management Power Our 24/7 World
By Lee Harrison - 11 Nov, 2025 - Comments: 0

Hey there, tech enthusiasts and digital pioneers! Have you ever stopped to think about the tiny, intricate components that keep our modern world humming? From the advanced safety features in your car to the massive data centers powering AI, semiconductors are truly the unsung heroes. But what happens when these tiny titans face immense pressure, like the non-stop demands of AI workloads? That's... » read more

Revolutionizing Chip Testing: Navigating Bottlenecks
By Vidya Neerkundar - 14 Oct, 2025 - Comments: 0

In today's rapidly evolving semiconductor landscape, System-on-Chips (SoCs) are becoming increasingly complex, integrating multiple processing cores, specialized accelerators and vast memory arrays. This escalating complexity, while enabling incredible functionality, presents significant challenges for Design-for-Test (DFT) engineers. Ensuring the thorough and efficient testing of these intrica... » read more

New Error Correcting Code And Non-Volatile Memory Options For Memory BIST
By Etienne Racine - 12 Aug, 2025 - Comments: 0

Tessent MemoryBIST from Siemens EDA provides a complete solution for at-speed test, diagnosis, repair, debug and characterization of embedded memories. Leveraging a flexible hierarchical architecture, built-in self-test (BIST) and self-repair can be integrated at both the individual core level and the top level. Tessent MemoryBIST efficiently addresses the ever-increasing demand for testing ... » read more

Addressing Silicon Lifecycle Scaling Demands
By Marc Hutner - 10 Jul, 2025 - Comments: 0

In today’s competitive business landscape, navigating complexity can be a decisive advantage, but it also presents significant challenges. Three crucial trends driving the rise of complexity are technology scaling, design scaling and system scaling. Traditionally, Design for Test (DFT) solutions have focused on the die level; however, these challenges present opportunities at the package and ... » read more

← Older posts

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2026 SMG   |  Terms of Service  |  Privacy Policy