New Error Correcting Code And Non-Volatile Memory Options For Memory BIST

Tessent MemoryBIST from Siemens EDA provides a complete solution for at-speed test, diagnosis, repair, debug and characterization of embedded memories. Leveraging a flexible hierarchical architecture, built-in self-test (BIST) and self-repair can be integrated at both the individual core level and the top level.

Tessent MemoryBIST efficiently addresses the ever-increasing demand for testing complex memory configurations by automating support for:

• Memory library mapping and validation
• DFT insertion flow
• Complex memory configurations support
• DFT architecture for optimized area

Memory BIST insertion may seem straightforward, but several aspects can significantly impact the quality of the memory BIST solution, especially for designs with many memory instances. Listed below are some of the considerations that could aid in the memory BIST decision-making process:

• Input from the physical floor planning stage of the design helps determine which memories can be grouped. Usually, these memories are physically placed near one another and can be accessed with the same controller.
• Which memories belong to which clock domain, which helps to determine the number of independent controllers needed. Memories are tested with memory BIST at their native operational frequency, so testing memories in the same clock domain with their independent controllers works best.
• Power dissipation requirements, which help in restricting how many memories can be tested in parallel.
• Memories might need special algorithms to be programmed during the memory BIST test. These algorithms are sometimes known pre-silicon; other times, they must be programmed post-silicon.
• Diagnostic resolution with memory test.

Inputs such as floor-planned memories (via a placement information file), power dissipation levels (specifying the maximum tolerated level) and correct clock domains (used during the functional operation of the memories) help Tessent MemoryBIST compute an optimal configuration. This configuration provides information on which memories can be grouped and tested with the desired number of memory BIST controllers and test steps.

Tessent MemoryBIST can be used to program specific algorithms pre-silicon (hard-coded algorithms), provide post-silicon programming capabilities (soft-coded algorithms) and support repairable memories. Several types of repair mechanisms are supported with Tessent MemoryBIST—including row only, column only, IO only, and row and column. Based on the required diagnostic capabilities (memory level, word level or bit level), the memory BIST hardware is generated and inserted into the design.

In addition to supporting stand-alone memories, Tessent MemoryBIST supports testing memories behind a shared-bus interface (often found in Arm cores).  A shared-bus implementation allows the designer to optimize the memory access bus for routing and timing and to provide the interface to which the DFT engineer connects the memory BIST controller. In this flow, the DFT engineer does not need to alter any functional logic connected to the memories. The figure below illustrates the shared-bus interface for a Tessent MemoryBIST controller.

Fig. 1: A single memory BIST controller can be shared between memories of a shared bus core.

On-chip-generated test patterns are delivered to the memories at application clock frequencies. The Tessent MemoryBIST controllers are configurable to support a variety of memory types, as well as a range of memory timing interfaces and memory port configurations. The controllers are accessed and controlled through an IEEE 1687-2014 (IJTAG) network. This highly configurable network is used to access all Tessent IP and can support any third-party IJTAG-compliant instruments. The controllers can be accessed throughout the life of the integrated circuit, including manufacturing test, silicon debug and in-system test.

Fig. 2: MRAM self-repair architecture.

As the memory content of today’s chips continues to grow, Tessent MemoryBIST significantly helps manage this complexity. At the International Test Conference India 2025, Siemens EDA announced two new options to this robust solution: Tessent MemoryBIST ECC and NVM.

The Tessent MemoryBIST ECC option complements memory repair to deliver the highest yield improvement for both production and post-silicon applications. This solution supports memories with a combination of spare resources and ECC capabilities. It is also possible to use ECC as the primary correction method when memories have no spare resources.

The ECC option enables the optimal combination of memory redundancy and ECC to be utilized during manufacturing and in-system tests. It does this by allowing the number of ECC bits for repair to be selected at runtime. During manufacturing, the ECC circuitry is turned off, and Tessent MemoryBIST verifies the integrity of the entire memory, including the array portion where ECC check bits are typically stored. Redundant or spare resources can be allocated where they are needed the most, leaving ECC capabilities to detect and correct occasional errors.

Tessent MemoryBIST ECC includes some industry-first benefits. It’s the first EDA-based BIST solution that supports memory repair, leverages the presence of ECC logic and delivers the highest yield improvement, not just for production but also post-silicon (in-system).

Fig. 3: Tessent ECC.

Tessent MemoryBIST ECC:

• Enhances reliability: Customizable pass/fail criteria allow for optimal use of memory redundancy and ECC
• Improves test quality: Memory locations holding ECC bits are tested with the same high-quality test algorithms as the rest of the standard data locations
• Safeguards against aging defects: Works with current and future ECC detection/correction capabilities

The Tessent MemoryBIST NVM option extends silicon-proven memory BIST test applications from SRAMs to MRAMs and other non-volatile memories (NVMs). It simplifies a DFT engineer’s work by automating NVM tests on-chip, performing automatic trim search settings for both manufacturing and in-system purposes. It streamlines what is usually a complex ATE test sequence into a task that can be accomplished using a lower-cost tester. Additionally, it identifies borderline low-quality devices and health monitoring to help address silent data errors and corruption. The Tessent MemoryBIST NVM option will be available in early 2026.

Tessent MemoryBIST NVM:

• Provides flexible test & repair: Automated application of NVM-specific algorithms supporting specialized access modes and ECC capabilities
• Decreases manufacturing test costs: Simple ATE test flow using fast on-chip trim calibration for optimal read and write operations
• Enhances reliability: Flags low-quality memory devices and allows health monitoring to track failures over time

Implementation of the most challenging DFT tasks is greatly simplified by the production-proven and widely adopted automation available in Tessent products. Tessent offers comprehensive solutions for integrated circuit (IC) testing and functional monitoring. These include top-tier tools designed for testing optimization, data analytics, security, debugging and in-life monitoring. Our products ensure maximum test coverage, accelerate yield ramp-up and enhance quality and reliability throughout the silicon lifecycle. To read more on Tessent MemoryBIST, please visit www.siemens.com/tessent-memorybist.