Analog Scan: Unlocking A New Era In Mixed-Signal Test

Anyone involved in IC product sign-off that includes a mixed signal design portion knows that developing robust tests for these intricate designs has historically been a significant bottleneck, no matter the application. It’s a hurdle many of us have faced, leading to extended development times, high costs, and sometimes an unsettling uncertainty about the true quality of our tests.

Traditionally, manufacturing tests for mixed-signal designs have relied heavily on functional, specification-based tests that validate datasheet parameters. While essential, this approach comes with its own set of challenges. Test development can be a long, drawn-out process, and the execution time on Automatic Test Equipment (ATE) can be substantial. This often translates to a test cost that’s an order of magnitude higher than that for the digital components of the chip – a significant burden on project budgets!

What’s more, the actual quality of these tests often remains a bit of a mystery. We typically express analog circuit coverage in terms of “datasheet coverage,” which, unfortunately, doesn’t always correlate directly to defects per million (DPPM). Many mixed-signal blocks also lack Design-for-Testability (DfT) features, leaving us with unknown defect coverage. While analog defect simulation offers a way to quantify this, it can become incredibly time-consuming and impractical for larger circuits with comprehensive spec-based tests. In many cases, we’ve had to rely on empirical determination of defect coverage, learned over time through design iterations and the analysis of field returns. It’s a method that works, but it’s far from ideal for today’s fast-paced development cycles.

A game-changer arrives: Introducing Analog Scan

But what if I told you there’s a revolutionary new approach that’s set to transform how we tackle mixed-signal testing? Siemens EDA has recently launched an innovative methodology designed to create highly efficient manufacturing mixed-signal tests that dramatically reduce both test costs and test escapes. This groundbreaking approach is called Analog Scan.

Analog Scan isn’t just another incremental improvement; it’s a paradigm shift. It requires the implementation of DfT within the circuit-under-test (CUT) to effectively inject stimulus signals and observe responses. What’s truly clever is that the inserted DfT circuitry isn’t placed in series with the signal propagation paths, ensuring it’s completely turned off during mission mode operations – zero impact on circuit’s normal operation.

The control and output of this DfT circuitry are connected to test data registers (TDRs), typically located outside the mixed-signal block. For testing, each analog input port is carefully driven to its DC operating point voltage. The generated test at the circuit level then employs a pseudo-random bit pattern set, with the functional clock of the CUT synchronized to the IJTAG clock. The voltages at the response nodes are then converted into single logic bits.

A critical aspect of Analog Scan is its robustness: each expected logic value from a response node is deemed invalid if it’s sensitive to process variations or noise. The PASS/FAIL criteria for these logic bits are determined through a reference simulation run conducted across various process corners of interest. This happens before any analog defect simulations, which are still instrumental for calculating defect coverage and optimizing your tests.

Digital simplicity, analog insight

One of the most exciting features of Analog Scan is its test protocol, which consists exclusively of digital test patterns. This digital nature allows for automatic retargeting to a chip’s top-level via an IJTAG infrastructure, including the generation of STIL test vectors. Imagine the simplicity and efficiency!

Unlike traditional functional tests, Analog Scan focuses on the structure of the circuit. Its only functional requirements relate to appropriate DC conditioning of analog ports and power rails. It specifically targets defects within each circuit element, adhering to the newly ratified IEEE 2427 Standard for Analog Defect Modeling and Coverage. This means Analog Scan provides a structural test that beautifully complements basic functional tests and, crucially, operates independently of the circuit’s functional specifications. Just like with digital scan tests, functional tests can still be used to top-up defect coverage, for trimming, and for mandatory tests, ensuring a comprehensive validation strategy.

A plethora of benefits await!

Analog Scan delivers across multiple dimensions:

• Massive test cost reduction — Analog Scan tests run orders of magnitude faster than spec-based tests on ATE, and analog defect simulation is significantly accelerated

• Lower instrumentation cost — Digital test patterns enable the use of low-cost digital ATE instrumentation

• Faster bring-up — First-silicon bring-up time is reduced thanks to the digital nature of the test patterns

• Higher defect coverage — Coverage figures achieved with Analog Scan typically exceed those from functional tests alone

• Better diagnosis — Analog Scan facilitates efficient diagnosis of field returns

Analog Scan is a feature provided by Tessent AnalogTest software and has been available since December 2025.