category: Silicon Lifecycle Management

category: IoT, Security & Automotive

On-chip Monitor Analytics Scales With Silicon Chip Production From NPI Through HVM
By Guy Cortez - 10 Jul, 2025 - Comments: 0

By Guy Cortez and Dan Alexandrescu At the New Product Introduction (NPI) stage of silicon chip production, product engineers work with a limited but critical dataset – typically from initial silicon samples or engineering lots – enabling early assessment of the power and performance of your silicon. Analytics solutions typically have no time-to-results (TTR) issues when the volume of dat... » read more

The Challenges Of Testing Automotive Chips
By Pawini Mahajan - 10 Jun, 2025 - Comments: 0

For as long as semiconductor devices have been around, motor vehicles have been one of the toughest operating environments. Chips in automobiles, trucks, and buses are subject to extremes of temperature, humidity, vibration, and radiation. The challenges of designing for these environmental conditions have grown more pronounced with advanced technology nodes, which are necessary to satisfy mark... » read more

Better ATPG To Minimize Chip Test Time And Cost
By Hari Mani - 08 May, 2025 - Comments: 0

As chips get ever bigger and more complex, the electronic design automation (EDA) industry must innovate constantly to keep up. Engineers expect every new generation of silicon to be modeled, simulated, laid out, and checked in about the same time with the same effort, despite the growth in die size and density. One area of particular focus is manufacturing test. Any effort expended to reduce t... » read more

Speeding Down Memory Lane With Custom HBM
By Faisal Goriawalla - 11 Mar, 2025 - Comments: 0

With the goal of increasing system performance per watt, the semiconductor industry is always seeking innovative solutions that go beyond the usual approaches of increasing memory capacity and data rates. Over the last decade, the High Bandwidth Memory (HBM) protocol has proven to be a popular choice for data center and high-performance computing (HPC) applications. Even more benefit can be rea... » read more

Hyperconvergence Of Design For Test And Physical Design
By Sri Ganta - 11 Feb, 2025 - Comments: 0

By Sri Ganta and Hyoung-Kook Kim In today’s highly competitive semiconductor industry, chip-design companies strive for competitive advantages by optimizing designs for PPA (Power, Performance, Area). Along with the functional logic, design cores also comprise DFT (Design for Test) logic that spreads across the design. The DFT logic also must be optimized for PPA, requiring design implemen... » read more

Power-Aware Test Vector Porting For Production ATE
By Hari Mani - 12 Nov, 2024 - Comments: 0

Power management in contemporary system-on-chip (SoC) designs is almost unimaginably complex. Processors and other chip cores turn on and off as needed. Advanced features such as dynamic voltage and frequency scaling (DVFS) can adjust to changing conditions and incrementally adjust power and performance on the fly. Power management starts from the lowest hardware level of transistor structures ... » read more

Advancements In Silicon Device Technology And Design Driving New SLM Monitor Categories
By Ash Patel - 15 Oct, 2024 - Comments: 1

Silicon, the foundation of modern electronics, has seen continuous advancements since the early days of integrated circuits. The pace of innovation has been driven by the relentless quest for miniaturization, increased performance, and efficiency. However, Moore’s Law is no longer a given and silicon is facing functional limitations as technology scales. To address these challenges and conti... » read more

Taking Data Center Serviceability To The Next Level
By Nozar Nozarian - 10 Sep, 2024 - Comments: 0

It is no secret that Artificial Intelligence (AI) workloads are driving an exponential growth in the scale of supercomputers and data centers. Training the latest LLM (Large Language Model), for instance, typically requires thousands of specialized processing cores running at full speed. As these models get more advanced with each generation, they need additional compute performance to absorb a... » read more

Are You Ready For HBM4? A Silicon Lifecycle Management (SLM) Perspective
By Faisal Goriawalla - 06 Aug, 2024 - Comments: 0

Many factors are driving system-on-chip (SoC) developers to adopt multi-die technology, in which multiple dies are stacked in a three-dimensional (3D) configuration. Multi-die systems may make power and thermal issues more complex, and they have required major innovations in electronic design automation (EDA) implementation and test tools. These challenges are more than offset by the advantages... » read more

Reducing Design Margins With Silicon Model Calibration
By Guy Cortez - 09 Jul, 2024 - Comments: 0

By Guy Cortez and Mark Laird It’s no secret to anyone that chip design gets harder every year. There are two major trends driving these ever-increasing challenges. The first is the continual scaling down to smaller design nodes. Although the pace of new node introduction has slowed somewhat in recent years, the impact of each new geometry and process is more dramatic than ever before. Acce... » read more

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