category: Silicon Lifecycle Management

category: Auto, Security & Edge AI

High-Speed Manufacturing And In-Field Scan Test Access Via PCI Express For GPIO Limited SoCs
By Ash Patel - 09 Jun, 2026 - Comments: 0

By Ash Patel and Shubharthi Datta, Synopsys, and Chuanyun Fan, Cisco Today’s huge, deep submicron system on chip (SoC) designs present many challenges at every stage of development, from architectural exploration to volume production. This post addresses the specific hurdle of effective and efficient manufacturing tests for these complex devices. It outlines a commercially available soluti... » read more

Complete End-To-End Closed-Loop Product Yield Ramp And Learning
By Guy Cortez - 12 May, 2026 - Comments: 0

By Guy Cortez and Maheshwaran Jothi Yield ramp has always been a concern in semiconductor manufacturing: systems companies need confidence that devices meet quality targets before shipment, and chipmakers need to reach yield entitlement quickly to control cost and supply. While this has never been easy, advanced nodes are raising the bar again. First, designs are larger and more heterogen... » read more

Enhancing Silicon Reliability With In-System Test And SLM Data
By Adam Cron - 07 Apr, 2026 - Comments: 0

Innovation in semiconductor development and manufacturing shows no signs of slowing down. Ever-larger chips at ever-smaller geometries create new challenges all the time. At the same time, competitive pressures are shrinking time to market (TTM) and putting enormous pressure on project teams. Furthermore, the wide use of electronics in safety-critical applications demands better reliability, av... » read more

Enabling Seamless Monitoring, Test, And Repair In Multi-Die Designs
By Yervant Zorian - 10 Mar, 2026 - Comments: 0

By Yervant Zorian and Sandeep Kumar Goel Anyone who follows the semiconductor industry knows that the accelerating performance, scale and energy efficiency demands of the AI revolution are outpacing the advances achievable by simply pushing the chip performance of monolithic, single-die designs. Multi-die design using 2.5D and 3D technologies has emerged as a necessity to keep the pace of in... » read more

Robust Dynamic Voltage Droop Mitigation And Power Management
By Graham Woods - 13 Jan, 2026 - Comments: 1

Power management is one of the keys for developing successful semiconductors products. There are virtually no applications for which power consumption is not a concern. Many creative solutions have been developed to reduce and manage power. Making these schemes work robustly in real-world conditions can be a challenge. This post considers widely used methods—voltage droop/glitch detection and... » read more

Scalable End-To-End Test Solutions For Today’s Complex SoCs
By Srikanth Venkat Raman - 17 Dec, 2025 - Comments: 0

By Srikanth Venkat Raman and Sri Ganta Today’s highly complex and large system on chip (SoC) devices and systems present many challenges to be addressed from manufacturing tests to the field while meeting stringent requirements for test costs, test quality, yield, debug, and turn-around-times. Scalable and efficient end-to-end test solutions that scale to large and complex SoC design cores... » read more

Expanding The Scope Of Testing In Complex Systems
By Nozar Nozarian - 14 Oct, 2025 - Comments: 0

Semiconductor devices now anchor the world’s most demanding infrastructures—from hyperscale data centers to advanced automotive platforms and industrial control systems. At scale, even rare faults can have significant cumulative impact, and the downstream consequences of failure extend far beyond a single board or rack. Unplanned outages translate into lost revenue, contractual penalties, f... » read more

Monitor, Test, And Repair For Multi-Die Health And Reliability
By Yervant Zorian - 09 Sep, 2025 - Comments: 0

Ever since the earliest semiconductor devices, silicon health has been a concern. Systems manufacturers wanted to be sure that their chips worked properly before being soldered onto printed circuit boards (PCBs). They put pressure on semiconductor suppliers to test wafers, individual dies, and assembled parts before they were shipped. A wide range of design-for-test (DFT) approaches were develo... » read more

Test Hyperconvergence In Semiconductor Development
By Pawini Mahajan - 12 Aug, 2025 - Comments: 0

Back when semiconductor devices contained only a few thousand gates, manufacturing test was almost an afterthought. The development team threw the chip “over the wall” to the test engineers, who developed a set of test patterns for the manufacturing floor. As this process became more automated and chips became more complicated, test considerations crept into the development flow and design-... » read more

On-chip Monitor Analytics Scales With Silicon Chip Production From NPI Through HVM
By Guy Cortez - 10 Jul, 2025 - Comments: 0

By Guy Cortez and Dan Alexandrescu At the New Product Introduction (NPI) stage of silicon chip production, product engineers work with a limited but critical dataset – typically from initial silicon samples or engineering lots – enabling early assessment of the power and performance of your silicon. Analytics solutions typically have no time-to-results (TTR) issues when the volume of dat... » read more

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