category: Silicon Lifecycle Management

category: IoT, Security & Automotive

Automotive Safety Requires PVT Monitoring IP Within Semiconductor ICs
By Rohan Bhatnagar - 12 Sep, 2023 - Comments: 0

The modern automobile, especially with the move toward more electrification, presents huge challenges to the designers of vehicular electronics. Gone are the days of mechanical issues and oil changes being primary concerns. Today’s automobile has a high number of semiconductor chips performing functions for self-driving autonomous systems, advanced driver assistance systems (ADAS), connectivi... » read more

Reducing Chip Test Costs With AI-Based Pattern Optimization
By Rahul Singhal - 31 Jul, 2023 - Comments: 0

The old adage “time is money” is highly applicable to the production testing of semiconductor devices. Every second that a wafer or chip is under test means that the next part cannot yet be tested. The slower the test throughput, the more automatic test equipment (ATE) is needed to meet production throughput demands. This is a huge issue for chip producers, since high pin counts, blazingly ... » read more

Ditch The Glitch
By Ramsay Allen - 11 Jul, 2023 - Comments: 0

To support the ever-growing performance demands of cutting-edge applications like automotive and hyperscaler, SoC complexity continues to increase. The emergence of multi-die technology has also compounded this complexity. To keep up with these demands, design-for-test (DFT) logic must also evolve to ensure greater levels of test robustness and silicon health. The “Shift left” concept which... » read more

The Ever-Increasing Role Of PVT Monitor IP And Its Significance In Silicon Lifecycle Management
By Rohan Bhatnagar - 05 Jun, 2023 - Comments: 0

The demand for semiconductor chips has grown exponentially over the years, driven by advancements in technologies such as artificial intelligence, the internet of things, 5G, automotive and cloud. With this increased demand, there is a growing need for more reliable semiconductor chips that can operate under extreme conditions and withstand the rigors of modern applications. Here are some of th... » read more

Silicon Lifecycle Management Advances With Unified Analytics
By Guy Cortez - 25 Apr, 2023 - Comments: 0

In a typical day in the life of a product engineer, they have gone through the requisite wafer sort testing in manufacturing with the next step to assemble the resultant good die into their respective packages. While performing a series of parametric tests during final test, yield issues are encountered and the process of finding the source of the issues begins. Luckily, with access to a good d... » read more

Power-Aware Test: Beyond Low-Power Test
By Rahul Singhal - 11 Apr, 2023 - Comments: 0

By Rahul Singhal and Likith Kumar Manchukonda Power consumption is one of the key considerations when designing today’s semiconductor chips and systems. Over the years, the constant need for higher performance and more functions from the chips has been driving the continuous requirement for higher transistor density. The process node scaling makes this possible by reducing transistor sizes... » read more

Compiler Optimization Made Easy
By Nozar Nozarian - 07 Mar, 2023 - Comments: 0

In a previous blog post, we discussed the benefits of using automation to maximize the performance of a system. One use case I mentioned was compiler flag mining, and the fact that performance is available beyond the standard optimization flags provided by most compilers. Getting to this untapped performance is a difficult problem to solve, but fortunately there is an easy way. A universe of o... » read more

Scan Pattern Portability From PSV To ATE To SLT To IST
By Ash Patel - 30 Jan, 2023 - Comments: 0

By Ash Patel and Karthik Natarajan Chip testing has become increasingly complex due to the number of variables impacting designs – from design size and complexity, to high transistor counts on advanced technology nodes, to 2.5D/3D packaging, to manufacturing variability. All of these combine to make testing today's chips and packages more complicated than ever before. The number of test pa... » read more

Testability Analysis Based On Ever-Evolving Technology
By Pawini Mahajan - 06 Dec, 2022 - Comments: 0

The complexity of system-on-chip (SoC) designs continues to grow, so the corresponding design-for-test (DFT) logic required for manufacturing has become more advanced. Design teams are challenged by high gate counts and an array of internally developed and third-party IP integrated into their designs. Understanding if one can create high-quality manufacturing tests for these complex designs mus... » read more

Automotive Applications Demand Silicon Lifecycle Management
By Pawini Mahajan - 08 Nov, 2022 - Comments: 0

Every electrical engineer learns early in university studies that automobiles are a highly demanding environment for electronics. Temperature and humidity extremes, noise and vibration, electrical interference, exposure to alpha particles, and other factors all make it hard to design and manufacture chips that will operate properly under all conditions. These challenges are exacerbated as chips... » read more

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