category: Silicon Lifecycle Management

category: IoT, Security & Automotive

Optimizing Vmin With Path Margin Monitors
By Ash Patel - 24 Oct, 2022 - Comments: 0

By Firooz Massoudi and Ash Patel Choosing the right operating voltage for various digital blocks within a semiconductor device is one of the most important tasks faced by chip designers. Operating voltage has major effects on performance, power consumption, and reliability. Increasing the voltage generally increases performance, but at the cost of more power and higher lifetime operating cos... » read more

Test Data Streaming For The Next Generation Of Designs
By Rahul Singhal - 08 Sep, 2022 - Comments: 0

Semiconductor chips have been evolving to meet the demands of rapidly transforming applications, and so has the test technology to meet the test goals of those chips. Going back two decades or so, the applications were limited and the designs were simpler, thus the concerns about power, performance and area (PPA), turn-around time, re-use and time-to-market, etc., were important but not as crit... » read more

Are You Leaving Performance On The Table? Here Is One Sure Way To Find Out
By Nozar Nozarian - 09 Aug, 2022 - Comments: 0

Compute platforms are always hungry for more performance. This is a fact that we simply cannot escape. Whether you are targeting high performance computing, IoT, mobile, or the automotive market, you need to unlock the best performance for your specific workloads. This relentless quest for performance comes with an unwelcome side effect: system complexity. As hardware becomes more capable, the ... » read more

Leverage Functional Interfaces For High-Speed Test Access During All Phases Of The Silicon Lifecycle
By Ash Patel - 12 Jul, 2022 - Comments: 0

Chip testing used to be straightforward. The development team used fault simulation to select a subset of the functional tests that could detect most possible manufacturing faults. These were translated to test patterns that ran on automated test equipment (ATE) to screen out defective dies at wafer test and bad packaged chips in final test. Lots of new technology was introduced over time, incl... » read more

Enabling SoC Visibility For Future Secure Hardware Architectures With In-Chip Environmental Monitoring
By Ramsay Allen - 07 Jun, 2022 - Comments: 0

Billions of people around the world are now online and generating vast amounts of data every day. This data revolution, which is largely driven by user performance requirements, is a double-edged sword. On one hand it is enabling huge technology advancements, revolutionizing the way we connect with each other and the world around us, but on the other hand it is exposing major vulnerabilities in... » read more

Closing The Post-Silicon Timing Analysis Gap
By Ash Patel - 10 May, 2022 - Comments: 0

Accurate static timing analysis is one of the most important steps in the development of advanced node semiconductor devices. Performance numbers are included in chip and system specifications from the earliest marketing requirements. The architects and designers carefully determine clock cycle times that can achieve the required performance using the chosen high-level architecture, micro-archi... » read more

Choosing The Right Server Interface Architectures For High Performance Computing
By Jerry Lotto - 12 Apr, 2022 - Comments: 0

The largest bulk and cost of a modern high-performance computing (HPC) installation involves the acquisition or provisioning of many identical systems, interconnected by one or more networks, typically Ethernet and/or InfiniBand. Most HPC experts know that there are many choices between different server manufacturers and the options of form factor, CPU, RAM configuration, out of band management... » read more

A Practical Approach To DFT For Large SoCs And AI Architectures, Part II
By Rahul Singhal - 08 Mar, 2022 - Comments: 0

By Rahul Singhal and Giri Podichetty Part I of this article discusses the design-for-test (DFT) challenges of AI designs and strategies to address them at the die level. This part focuses on the test requirements of AI chips that integrate multiple dies and memories on the same package. Why 2.5D/3D chiplet-based designs for AI SoCs? Many semiconductor companies are adopting chiplet-based d... » read more

Is A Guestimate Good Enough For Obtaining Failure Mode Distribution?
By Jamileh Davoudi - 08 Feb, 2022 - Comments: 0

SoCs targeting automotive applications are required to meet certain safety and quality standards as described in ISO 26262. A quantitative approach to safety analysis involves performing Failure Mode Effects and Diagnostic Analysis (FMEDA). FMEDA is a systematic quantitative analysis technique to obtain subsystem/product level failure rates, failure modes and diagnostic capabilities of systemat... » read more

A Practical Approach To DFT For Large SoCs And AI Architectures, Part I
By Rahul Singhal - 11 Jan, 2022 - Comments: 0

The traditional processors designed for general-purpose applications struggle to meet the computing demands and power budgets of artificial intelligence (AI) or machine leaning (ML) applications. Several semiconductor design companies are now developing dedicated AI/ML accelerators that are optimized for specific workloads such that they deliver much higher processing capabilities with much low... » read more

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