category: Videos

category: IoT, Security & Automotive

Big Changes In Optical Inspection
By Ed Sperling - 16 Oct, 2024 - Comments: 0

Optical inspection always has been the workhorse technology for finding defects in chips. It's fast, cost-efficient, and generally reliable enough for most chips. But as logic scales into the angstrom range, and as systems become collections of chiplets, optical inspection needs to be combined with other types of inspection such as X-ray and acoustic. Kyle Vander Schaaf, application engineer at... » read more

Real-Time Safety Monitoring
By Ed Sperling - 28 Aug, 2024 - Comments: 0

Various types of semiconductor test will determine whether a chip is free of defects and meets the specification, but understanding how it's behaving in the field under real workloads and harsh ambient conditions may be very different in automotive applications, where vibration, heat, cold can disrupt the normal functioning of a chip over time and reduce its lifespan. Alex Burlak, vice presiden... » read more

Making Adaptive Test Work Better
By Ed Sperling - 10 Jun, 2024 - Comments: 0

One of the big challenges for IC test is making sense of mountains of data, a direct result of more features being packed onto a single die, or multiple chiplets being assembled into an advanced package. Collecting all that data through various agents and building models on the tester no longer makes sense for a couple reasons — there is too much data, and there are multiple customers using t... » read more

Overlay Optimization In Advanced IC Substrates
By Ed Sperling - 29 Apr, 2024 - Comments: 1

Overlay is becoming a significant problem in the manufacturing of semiconductors, especially in the world of advanced packaging substrates — think panels — the larger the area, the greater the potential for distortion due to warpage. Solving this issue requires more accurate models, better communication through feed forward/feed back throughout the flow, and real-time analytics that are bak... » read more

Cost And Quality Of Chiplets
By Ed Sperling - 19 Mar, 2024 - Comments: 0

Chiplets add a whole new challenge for the semiconductor industry. How much testing is enough? How do you optimize system binning? What’s the right amount of burn-in? The answers to these questions will vary, depending upon cost and quality tradeoffs, the number and source of the chiplets, and real-world workloads and projected lifespans. Marc Jacobs, senior director of solutions architectur... » read more

Yield Tracking In RDL
By Ed Sperling - 07 Feb, 2024 - Comments: 0

Yield is a much bigger issue when it comes to panel-level packages, which may contain up to 24 RDL layers. Just finding the defects is a massive challenge, let alone understanding how they will impact the entire device. Many of these advanced packages are being used in data centers for generative AI, and killer defects caused by bridges and opens can cause serious problems. What happens, for in... » read more

Reducing Power In Data Centers
By Ed Sperling - 16 Jan, 2024 - Comments: 0

The rollout of generative AI, coupled with more data in general, is requiring data centers to run servers harder and longer. That, in turn, is generating more heat and accelerating aging, and to ensure these systems continue working over their projected lifetimes, chipmakers are building extra margin into chips. That increases the amount of energy required to run and cool them, and it can short... » read more

Using Deep Data For Improved Reliability Testing
By Ed Sperling - 08 Jan, 2024 - Comments: 0

Reliability testing always has been a challenge for semiconductor companies, but it’s becoming much more difficult as devices continue to shrink, as they’re integrated together in advanced packages, and as they’re utilized under different conditions with life expectancy that varies by application and use case. Nir Sever, senior director of business development at proteanTecs, and Luca Mor... » read more

Total Overlay With Multiple RDLs
By Ed Sperling - 13 Nov, 2023 - Comments: 0

As Advanced IC Substrates (AICS) add more RDL layers, requiring additional via connections between the RDL layers, the potential for cumulative overlay shift increases. This overlay shift can lead to longer RDL traces, which increases interconnect resistance, resulting in lower yield. Keith Best, director of product marketing, for lithography at Onto Innovation, talks about total overlay — th... » read more

Manual X-ray Inspection
By Ed Sperling - 28 Aug, 2023 - Comments: 0

Increased density in advanced node chips and advanced packaging offers a way to greatly improve performance and reduce power, but it also makes it harder to inspect these devices for real and latent defects. Higher density can lead to scattering of light, and heterogeneous integration in a package means it’s not always possible to see through all materials equally. Chris Rand, product line ma... » read more

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