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Re-using Common Simulation Set-Up Processes To Speed Regression


Functional verification of SoCs always has some kind of set up process. For complex SoCs, at least, this initial set up phase often consumes from 20 to 90% of each test’s total simulation time. And thousands of tests are run in the verification of a design. This set up phase could be either executing the exact same sequence of simulation steps, or programming the design to reach the same i... » read more

Solving Puzzling Power-Aware Coverage: Getting An Aggregated Coverage Metric


Coverage metrics tell us when a design has been thoroughly verified, or at least exercised to the point of diminishing returns. Rarely can every design artifact or design parameter of a highly complex design be covered 100 percent, but we can use coverage metrics to know the extent to which we have verified the design — enough to be confident that it will function as desired in the end produc... » read more

Updated UVM Cookbook Supports IEEE 1800.2 Standard And Emulation


I’m happy to announce that we at Mentor have just released a fully-updated version of our popular UVM Cookbook, which is available online here. Cookbook Overview Diagram The Universal Verification Methodology (UVM) is a standard library of SystemVerilog classes that supports a modular, reusable testbench architecture for constrained-random functional verification. Meanwhile, Mentor’... » read more

Power-Aware Static Checks: Static Checker Results And Debugging Techniques


In Part 1 of this three article series on power aware (PA) verification, we examined the foundations and verification features of PA static checks. In Part 2, we discussed the features of the static verification library and described best static verification practices. Part 3 concludes this series with details of static PA verification tool procedures using a real example to analyze PA-Stati... » read more

Three Steps To Low Power Coverage Closure


By Awashesh Kumar and Madhur Bhargava Low-power design and verification is becoming more complex. Yet it is critical that all power elements are verified, and it is even more important to verify the complex interactions between these elements at a high abstraction level. However, power-aware coverage closure is difficult to attain and complex by nature. Existing low-power coverage methodo... » read more

Optimizing Your DRC Debug Can Reap Big Productivity Gains


Debugging design violations found by design rule checking (DRC) has always taken a significant share of the time needed to get a design to tapeout. And debug time only increases as the number and complexity of DRC expands with each new process node. Any steps you can take to make your DRC debug process more efficient directly improves your productivity. One technique for minimizing debug tim... » read more

Power-Aware Intent And Structural Verification Of Low-Power Designs


In Part 1 of this series on power aware (PA) verification, we examined the foundations and verification features of PA static checks. In Part 2, we will discuss the features of the static verification library and describe best static verification practices. Library for Static Verifications Cell-level and pin-level attributes from Liberty are mandatorily required for accurate PA-Static verif... » read more

Power Aware Intent And Structural Verification Of Low-Power Designs


Power aware static verification, more popularly known as PA-Static checks, is performed on designs that adopt certain power dissipation reduction techniques through the power intent or [gettech id="31044" t_name="UPF"]. The term static originates from verification tools and methodologies that applies a set of pre-defined power aware (PA) or multi-voltage (MV) rules based on the power requiremen... » read more

How Robust Is Your ESD Protection? Are You Sure?


Electrostatic discharge (ESD) protection is critical at advanced nodes to safeguard designs against effects intensified by shrinking transistor dimensions and oxide layer thicknesses. On the other hand, ESD protection checks are consuming vastly more runtime and memory due to the growing die sizes of system-on-chips (SoCs) and the number of transistors they can hold. Designers are facing increa... » read more

A Simple Way To Improve Automotive In-System Test


The remarkable growth in automotive IC design has prompted a focus on ISO26262 functional safety compliance, which includes both high-quality manufacturing test and a minimum stuck-at test coverage of 90% for in-system test. Designers must also control IC test data volumes, test application times, and test costs. A new test point technology that improves in-system test coverage and reduces patt... » read more

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