High-Level Synthesis Propels Next-Gen AI Accelerators


Everything around you is getting smarter. Artificial intelligence is not just a data center application but will be deployed in all kinds of embedded systems that we interact with daily. We expect to talk to and gesture at them. We expect them to recognize and understand us. And we expect them to operate with just a little bit of common sense. This intelligence is making these systems not just ... » read more

How To Get Accurate Inductance Extraction For Superconductor ICs


By Hossam Sarhan and Dusan Petranovic Supporting the high performance and reliability needed for artificial intelligence (AI), data centers and cloud computing requires powerful and efficient integrated circuits (ICs). More semiconductor companies are considering superconductor ICs for their unique properties that allow ultrafast processing of digital information. These properties include fa... » read more

The City In The Tower: 3D ICs Transform The Electronics System Landscape


By Keith Felton and Todd Burkholder The time of 3D integrated circuits (3D ICs) is here, and they will revolutionize the semiconductor industry and effect a watershed in the nature of electronics products that can be designed and manufactured. Yet again—as with personal computers, the internet, and smart phones—our increasingly digital world will never be the same. 3D IC architectures... » read more

The Seven Pillars Of IC Package Physical Design


Today’s heterogeneously integrated semiconductor packages represent a breakthrough technology that enables dramatic increases in bandwidth and performance with reduced power and cost compared to what can be currently achieved in traditional monolithic SoC designs. Figure 1. A heterogeneously integrated device with 47 chiplets. (Image Source: Intel) The evolving landscape of packagin... » read more

AI-Driven Macro Placement Boosts PPA


In the era of EDA 4.0, artificial intelligence (AI) and machine learning (ML) are transforming what electronic design automation tools are capable of. For many of the challenges of physical IC design, AI can provide significant benefits to both the turnaround time and the quality of the design, as measured by performance, power, and area (PPA) metrics. One implementation step due for improve... » read more

RTL Optimization Best Practices Help To Achieve Power Goals And Identify Reliability Issues Earlier


Designers face enormous challenges for low-power designs. Whether it is IoT at the edge, AI in the datacenter, robotics or ADAS, the demand for increased functionality and higher performance in SoCs is rapidly stretching power budgets to their breaking point. Power must be considered at every stage of chip design. Waiting to address power until late in the design cycle – post-netlist or durin... » read more

Do You Really Understand The Importance Of Parasitic Extraction In Chip Designs?


By Susanne Lachenmann and Petya Aleksandrova, Infineon Technologies, and Karen Chow, Siemens EDA One of the biggest challenges integrated circuit (IC) designers face in today’s complex designs is effectively managing the effects of parasitic elements such as resistance, capacitance, and inductance. Parasitic elements can significantly impact chip performance of a chip, making it critical f... » read more

No Hot Products


While marketers strive to launch the next “hot” product, engineers struggle to prevent literally hot products! A recent breakthrough in thermal modeling comes just in time as electronic component manufacturers and their OEM customers increasingly battle thermal design issues. Analog electronic component manufacturers have traditionally provided models in SPICE format so customers can sim... » read more

Fast, Accurate, Automated Via Insertion During Design Implementation Requires Foundry Rule Compliance


As the scaling of silicon technology proceeds, via resistance is becoming a dominant factor in integrated circuit (IC) yield, performance, and reliability. At advanced nodes, interconnects and via dimensions decrease, while the number of metallization layers increases. To moderate the impact of via resistance on yield and reliability and reduce electromigration (EM) and voltage drop (IR) effect... » read more

A New Approach To Design-Stage Layout Optimization Can Speed Time To Tapeout While Improving Power Management


The right tool for the job makes all the difference. Ever try hammering a nail in with a rock? How many nails did you ruin before you gave up? Or try to tighten a crucial bolt by hand? It takes forever, and you just can’t tighten it enough, so everything’s still kind of wobbly? Yeah, that’s kind of what it’s like trying to use an electronic design automation (EDA) tool to do a job it’... » read more

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