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Moving Past “It Works” — Intelligent Optimization Is the Key to PCB Excellence
By Shivani Joshi - 14 Aug, 2025 - Comments: 0

In the fast-evolving field of electronic systems design, engineers are under increasing pressure to deliver innovative, high-performance products within ever-shrinking development cycles. Traditional methods—relying on intuition, trial-and-error testing, and even basic simulation—struggle to keep pace with the growing complexity of modern systems. Nowhere is this more evident than in printe... » read more

A Better Path To Better 3D-IC Thermal Modeling
By Andras Vass-Varnai - 17 Jul, 2025 - Comments: 0

By Andras Vass-Varnai, Lee Wang, John Parry, Byron Blackmore, and Sudarshan Deo In an era where artificial intelligence, autonomous vehicles, and high-performance computing push the boundaries of semiconductor technology, the thermal management of 2.5D and 3D integrated circuits has become a make-or-break factor in product success. The traditional approach of treating thermal analysis as an ... » read more

Smarter, Faster, Leaner: Rethinking Verification For The Modern Era
By Harry Foster - 12 Jun, 2025 - Comments: 0

Verification isn’t just another step in the semiconductor design process—it’s increasingly the step that defines whether teams hit their schedules or miss the mark. With skyrocketing design complexity, accelerated development timelines, and persistent engineering shortages, the industry is feeling the pressure. Traditional methods aren’t keeping pace. At Siemens, we’ve been rethink... » read more

Best Practices For Power-Aware Verification: Because Designing For Low Power Is Only Half The Battle
By Chandu Challapalli - 15 May, 2025 - Comments: 0

As modern chips push the limits of power efficiency, power management has become a top priority. With today’s increasingly complex devices, verifying power intent isn’t just a technical requirement. It’s a necessity for building reliable silicon. One of the most important lessons learned in recent years is that RTL and power intent must evolve together. Treating power intent as a post... » read more

Fulfilling 3D-IC Trade-Off Analyses (And Benefits) With An AI Assist
By Pratyush Kamal - 13 Mar, 2025 - Comments: 0

As we walk around with supercomputers in our pockets and work at desks on even more powerful supercomputers, a lot of processing has moved to the cloud. As a politician described, this can be problematic on a day when there are no clouds in the sky. The world discovered the truth of those words when Crowdstrike struck on July 19, 2024. System designers who spent years balancing power, performan... » read more

Controlling Leakage Power
By Matthew Hogan - 17 Feb, 2025 - Comments: 0

IC designers face a significant challenge in managing leakage power - a phenomenon that can profoundly impact your device's power, performance, area (PPA), and overall reliability. Leakage can occur in various ways, from parasitic leakage to analog gate leakage or digital gate leakage, and you must address these issues with great care, as even subtle circuit changes can lead to reliability prob... » read more

Tame IR Drop Like Google
By Jeff Wilson - 16 Jan, 2025 - Comments: 0

In the relentless pursuit of semiconductor performance and efficiency, tech giants like Google are constantly pushing the boundaries of what's possible. As they scale their designs to the cutting-edge 3nm node, power integrity has emerged as a critical challenge that must be overcome. Enter Calibre DesignEnhancer (DE), Siemens' analysis-based solution for enhancing design reliability and man... » read more

Addressing Reset Tree Design Challenges For Complex SoCs With Advanced Structural Checks
By Reetika - 12 Dec, 2024 - Comments: 0

As SoC designs continue to evolve, the complexity of reset architectures has grown significantly. Traditionally, clock tree synthesis has been a major focus due to timing challenges, but now reset trees demand equal attention. With multiple reset sources, designers must deal with reset trees that can be more intricate than clock trees. Errors within a reset tree can lead to serious issues, incl... » read more

Harnessing Computational Storage For Faster Data Processing
By Ujjwal Negi - 14 Nov, 2024 - Comments: 0

By Ujjwal Negi and Prashant Dixit In the evolving landscape of data storage, computational storage devices (CSDs) are revolutionizing how we process and store data. By embedding processing capabilities within storage units, these devices enable in-situ data manipulation, minimizing data movement between storage and CPUs and dramatically improving performance and efficiency. This paradigm shi... » read more

Boost High-Performance IC Design Flows With Early Interactive Symmetry Checking
By Sara Khalaf - 17 Oct, 2024 - Comments: 0

In the realm of high-performance IC (integrated circuit) design, symmetry is not just an aesthetic preference—it’s a critical factor for ensuring proper device functionality, especially in analog and RF designs. Achieving symmetry early in the design process helps to ensure consistent electrical behavior, which is essential for meeting performance goals and maintaining device reliability. H... » read more

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