Thermal Issues And Modern SoCs: How Hot Is Hot?

A Q&A with Moortec CTO Oliver King. What are the thermal issues of modern SoCs? Gate density has been increasing with each node and that pushes up power per unit area, and I think that has become an even bigger issue with FinFET processes where the channels are more thermally isolated than the planar processes before them. In the last few planar nodes, leakage was an issue which led ... » read more

Power/Performance Bits: Mar. 13

Wireless charging Engineers at the University of Washington developed a method to safely charge a smartphone wirelessly using a laser, potentially as quickly as a standard USB cable. Safety features of the system include a reflector-based mechanism to shut off the laser and heatsinks. The charging beam is generated by a laser emitter that the team configured to produce a focused beam in the... » read more

Why Inductance Is Good for Area, Power and Performance

By Magdy Abadir and Yehea Ismail For chips designed at advanced technology nodes, interconnect is the dominant contributor towards delay, power consumption, and reliability. Major interconnects such as clock trees, power distribution networks and wide buses play a significant role in chip failure mechanisms such as jitter, noise coupling, power distribution droops, and electro-migration. ... » read more

Multiphysics Reliability Signoff For Next-Gen Auto Electronics Systems

The automotive industry is in the midst of a sea change. Growing market needs for electrification, connectivity on the go, advanced driver assistance systems, and ultimately the goal of autonomous driving, are creating newer requirements and greater challenges. A chassis on four wheels is now fitted with cameras, radar and other sensors, which will be the eyes of the driverless car, as well as ... » read more

Exponentials At The Edge

The age of portable communication has set off a scramble for devices that can achieve almost anything a desktop computer could handle even five years ago. But this is just the beginning. The big breakthrough with mobile devices was the ability to combine voice calls, text and eventually e-mail, providing the rudiments of a mobile office-all on a single charge of a battery that was light enou... » read more

Heterogeneous Hubbub

It’s no secret that designers today would prefer not to be restricted in their architectural choices. And who can blame them? At the same time, this sentiment has boosted interest and usage of both heterogenous architectures as well as the RISC-V ISA. To support this, companies across the design, test and verification ecosystem are ramping efforts. One such effort is the teaming of UltraSo... » read more

Power Aware Intent And Structural Verification Of Low-Power Designs

Power aware static verification, more popularly known as PA-Static checks, is performed on designs that adopt certain power dissipation reduction techniques through the power intent or [gettech id="31044" t_name="UPF"]. The term static originates from verification tools and methodologies that applies a set of pre-defined power aware (PA) or multi-voltage (MV) rules based on the power requiremen... » read more

32GT/s PCI Express Design Considerations

Today’s networking and rapidly emerging artificial intelligence (AI) applications are requiring more bandwidth in accelerators and GPUs, as well as faster interconnects to transmit and receive greater amounts of data. Towards the middle of 2017 the PCI-SIG industry consortium announced its latest specification, PCIe 5.0, which raised the data rate from 16GT/s to 32GT/s and doubled the link... » read more

The Analog Design Gap

By Benjamin Prautsch and Torsten Reich Sensors are everywhere. In the context of Industry 4.0 and IoT, we face an ever-increasing demand for high-quality sensing. Data acquisition is fundamental to adaptive production chains. So aggregating data isn't just some nice-to-have feature. It is the basis of modern production systems. But don’t we have sensors already? Isn’t everything fine?... » read more

Why All Nodes Won’t Work

A flood of new nodes, half-nodes and every number in between is creating confusion among chipmakers. While most say it's good to have choices, it's not clear which or how many of those choices are actually good. At issue is which [getkc id="43" kc_name="IP"] will be available for those nodes, how that IP will differ from other nodes in terms of power, performance, area and sensitivity to a v... » read more

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