Performance Analysis Of Electric Motors For EV Powertrains


Developing a battery EV powertrain is a complex systems problem. This technical paper examines the design and development of electric motors in an EV powertrain, showing how the different design choices — such as motor topology, winding type and cooling system — can be compared and evaluated considering their overall system impact. ANSYS Motor-CAD simulations can help engineers determine wh... » read more

LonWorks + BACnet: Multi Protocol Field Bus Solution


A fully interoperable multi-protocol field bus implemented by Adesto's partner Western Allied combines two popular Smart Building protocols in a single network. This whitepaper explains how. » read more

Addressing Pain Points In Chip Design


Semiconductor Engineering sat down to discuss the impact of multi-physics and new market applications on chip design with John Lee, general manager and vice president of ANSYS' Semiconductor Business Unit; Simon Burke, distinguished engineer at Xilinx, Duane Boning, professor of electrical engineering and computer science at MIT; and Thomas Harms, director EDA/IP Alliance at Infineon. What foll... » read more

Verdi Transaction Debug Solution: Unified Performance Analysis And Debug For Interconnect


In modern systems on chip (SoCs), where Arm AMBA protocols are intensively used as standard intellectual property (IP) interfaces, the interconnect is usually required to bridge and facilitate the communication between many different IP interfaces. The interconnect presents one of the biggest challenges of SoC verification, considering the different kinds of protocol interfaces, conversion of d... » read more

Addressing The Challenges Of Reset Verification In SoC Designs


This paper presents commonly occurring challenges involved in reset tree verification and their solutions. We lay out a three part approach to build a complete solution that combines static analysis of the design structure, RTL simulation with X-propagation, and formal verification. The paper includes results from testing this solution on a customer design. To read more, click here. » read more

Power/Performance Bits: Nov. 11


Smaller DACs and ADCs Researchers at the National University of Singapore invented a novel class of Digital-to-Analog (DAC) and Analog-to-Digital Converters (ADC) that use a fully-digital architecture. This digital architecture means design time for sensor interfaces can be reduced from months to hours with a fully-automated digital design methodology, the team said. It also has the benefit... » read more

Power/Performance Bits: Nov. 5


Conductive yarn Researchers at Drexel University created an electrically conductive coating for yarn that withstands wearing, washing, and industrial textile manufacturing. Rather than using metallic fibers, the coating is made up of different sized flakes of the two-dimensional material MXene, which was applied to standard cellulose-based yarns. Titanium carbide MXene can be produced in f... » read more

Accelerating Chiplets With 112G XSR SerDes PHYs


The fading of Moore’s Law and an almost exponential increase in data is challenging the semiconductor industry as never before. Indeed, zettabytes of data are constantly generated by a wide range of devices including IoT endpoints such as vehicles, wearables, smartphones and appliances. Moreover, sophisticated artificial intelligence (AI) and machine learning (ML) applications are adding new ... » read more

Tricky Tradeoffs For LPDDR5


LPDDR5 is slated as the next-gen memory for AI technology, autonomous driving, 5G networks, advanced displays, and leading-edge camera applications, and it is expected to compete with GDDR6 for these applications. But like all next-gen applications, balancing power, performance, and area concerns against new technology options is not straightforward. These are interesting times in the memory... » read more

Power/Performance Bits: Oct. 29


Chip scanning Researchers at the University of Southern California and the Paul Scherer Institut in Switzerland developed an x-ray technique to non-destructively scan chips to make sure they conform to specifications. Such a system could be used to identify manufacturing defects or malicious alterations, the team said. Called ptychographic x-ray laminography, the technique utilizes x-rays f... » read more

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