Demystifying Mirror Types


I’m not talking about carnival funhouse mirrors, but rather the different options for mirroring symbols, vias, and bond fingers in your IC Package layout. The Allegro Package Designer Plus and SiP Layout tools have two distinct styles of mirroring which are used in different places. Often, I get questions about what, exactly, those differences are. And even more, why the styles are used for d... » read more

Moore And More


For more than 50 years, the semiconductor industry has enjoyed the benefits of Moore's Law — or so it seemed. In reality, there were three laws rolled up into one: Each process generation would have a higher clock speed at the same power. This was not discovered by Moore, but by Dennard, who also invented the DRAM. Process generations continue to get faster and lower power, but the power... » read more

Brains And Computers At The VLSI Design Conference


One of the industry’s biggest events, the VLSI Design Conference, took place in Bangalore last week. This conference does a round-robin of cities, and this was the 10th time in its 33-year history that Bangalore was hosting it (the last time was in 2015). This year’s conference attracted over 1,800 technologist and leaders over five days – a huge turnout for this growing industry. Inci... » read more

System-in-Package For Heterogeneous Designs


System integration is increasingly being done using 3D packaging technologies rather than integrating everything onto a huge SoC. One motivation is the ability to not just to split up a design in a single process, but to package die from different processes. Sometimes there are economic reasons. Several presentations at HOT CHIPS had a partition of the design into the processor itself, and a... » read more

Mary Jane Irwin Receives The Kaufman Award


Mary Jane Irwin just got back from a cruise around the Greek islands with her husband of 53 years to celebrate being the first woman to receive the Kaufman award. When I wrote my post The 2019 Kaufman Award Goes to Mary Jane Irwin about her receiving the awards last week, I mostly just used the boilerplate biographical information from the press release. But that's rather dry, so I called her u... » read more

Scan Compression Is No Longer About Compression


Scan compression was introduced in the year 2000 and has seen rapid adoption. Nearly every design’s test methodology today implements this technology, which inserts compression logic in the scan path between the scan I/Os and the internal chains. In this article, we take a critical look at the technology to understand how scan compression has matured. The road to scan compression Since th... » read more

IC Test: Doing It At The Right Place At The Right Time


In the real world, we are slaves to our environment. The decisions we make are dependent on the resources available at any given time. In school, I remember coming up with a binary decision diagram (BDD) variable-ordering algorithm that relied on partial BDDs. Was that the best algorithm to determine the variable ordering of a BDD for a design? Probably not. However, it was easy to do as a coll... » read more

Psst, Says 5G… Wanna See What My New Antenna Tech Challenge Looks Like?


5G offers incredible potential, enabling 1000X more traffic, 10X faster speeds and an increase in the device battery capacity by 10X! So why hasn’t 5G technology been rolled out yet? The benefits all sound great, but there are also some challenges that need to be addressed. 5G is destined to cause a revolution around the world with burgeoning industries like autonomous driving, internet of... » read more

Processors Are Exciting Again


Today is a very exciting time in the world of processor architectures. Domain-specific processor architectures are now fully realized as the best answers to the challenges of low power and high performance for many applications. Advancements in artificial intelligence are leading the way to exciting new experiences and products today and in our future. There have been more advances in deep lear... » read more

Designers Face Growing Problems With On-Chip Power Distribution


The technology evolution in semiconductor manufacturing has led to chips with ever-higher power densities, which is leading to serious problems with on-chip power distribution. Specifically, the problems surrounding voltage drop—or IR drop (from V=IxR)—have become so acute that we have seen multiple companies starting to get back dead silicon from the fab. For example, a recent 7nm chip ... » read more

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