Integrating Energy Efficiency Considerations Into Your Design From The Beginning


Data center networking is responsible for consuming about 1% of the global electricity supply. With the advent and integration of AI into various sectors, the pressure on both hardware and software infrastructures, necessitated by neural networks and extensive language models, is expected to increase significantly. The burgeoning energy consumption by hyperscale data centers emerges as an ur... » read more

Verifying Hardware Security With RTL Simulation


When consumers think about security for their electronic gadgets, financial applications probably spring first to mind. Identity theft and unauthorized access to bank and investment accounts are a constant threat. But there’s more to worry about every day. Stories of webcams and smart speakers being hacked are all over the web. Users rightfully demand that device manufacturers provide a high ... » read more

Impact Of 3DHI On Aerospace And Government Applications


By Ian Land, Kenneth Larsen, and Rob Aitken With challenging size, weight, and power (SWaP) requirements, chip designs for aerospace, defense, and government applications are a unique breed. No surprise here, considering systems like satellites and submarines must operate reliably in the distinctly harsh environments of outer space and ocean depths, respectively. Given the SWaP criteria a... » read more

Getting Optimal PPA For HPC & AI Applications With Foundation IP


By Andrew Appleby, Xiaorui Hu, and Bhavana Chaurasia The demand for application-specific system-on-chips (SoCs) for compute applications is ever-increasing. Today, the diversity of requirements means there is a need for a rich set of compute solutions in a wide range of process technologies. The resulting products may have very different but demanding power, performance, and area (PPA) requi... » read more

Advanced Design Debug Demands Integrated Verification Management


Design verification has been the dominant portion of chip development for years, and the challenges grow bigger every day. Single dies continue to grow in transistor count and complexity. Advanced techniques such as 2.5D and 3D multi-die systems and emerging technologies such as wafer-scale integration pack even more transistors and functionality into a single device. This situation has created... » read more

Latency Considerations For 1.6T Ethernet Designs


Since its 1980s debut with 10Mbps shared LANs over coaxial cables, Ethernet has seen consistent advancements, now with the potential to support speeds up to 1.6Tbps. This progression has allowed Ethernet to serve a wider range of applications, such as live streaming, Radio Access Networks and industrial control, emphasizing the importance of reliable packet transfer and quality of service. With... » read more

Using Virtual Metal Fill To Predict The Impact Of High Level Nets


A recent blog post discussed the use of virtual metal fill (VMF) to predict the effects of real metal fill when performing RC extraction on a chip layout. This enables static timing analysis (STA) closely correlated with final post-fill results without incurring the time to perform the actual metal fill insertion during the layout-STA loop. VMF is fast enough to be run in every iteration of thi... » read more

Developing Energy-Efficient AI Accelerators For Intelligent Edge Computing And Data Centers


Artificial intelligence (AI) accelerators are deployed in data centers and at the edge to overcome conventional von Neumann bottlenecks by rapidly processing petabytes of information. Even as Moore’s law slows, AI accelerators continue to efficiently enable key applications that many of us increasingly rely on, from ChatGPT and advanced driver assistance systems (ADAS) to smart edge device... » read more

Evolution Of Equalization Techniques In High-Speed SerDes For Extended Reaches


The relentless demand for massive amounts of data is accelerating the pace of high-performance computing (HPC) within the high-speed Ethernet realm. This escalation, in turn, intensified the complexity associated with designing networking SoCs, including switches, NICs, retimers, and pluggable modules. Such growth is accelerating the demand for bandwidth hungry applications to transition from 4... » read more

Using Virtual Metal Fill To Solve Real Design Problems


People learning about semiconductor manufacturing might well be confused by the concept of metal fill. It seems perfectly intuitive that laying out a complex chip will result in some regions with fewer transistors and metal interconnect than others. It makes sense that there will be areas that are mostly empty. So why spend money on more complicated masks and on extra metal just to fill those e... » read more

← Older posts