category: IP And LP In SoCs

category: Auto, Security & Edge AI

Cloud HPC For AI: Addressing Latency, Cost, And Scale At The Architectural Level
By Sumit Vishwakarma - 22 Jun, 2026 - Comments: 0

Many organizations assume that moving HPC workloads to the cloud is simply a matter of lifting and shifting on-premises clusters. In practice, that approach often erodes performance, inflates costs, and undermines AI training efficiency. Getting the most out of HPC in the cloud requires a fundamentally different architectural approach — one that minimizes latency, maximizes utilization, an... » read more

Re-Architecting Die-to-Die IO For AI
By Lakshmi Jain - 11 Jun, 2026 - Comments: 0

By Lakshmi Jain and Wei-Yu Ma As AI-driven workloads continue to push the boundaries of compute scale, power efficiency, and bandwidth density, conventional die-to-die interconnect technologies—such as SerDes-based links and wide parallel IO—are increasingly becoming limiting factors. These approaches struggle to meet the growing demands for higher bandwidth density and improved energy e... » read more

Early HBM4 Validation Points The Way For Next Generation AI And HPC Systems
By Brett Murdock - 09 Apr, 2026 - Comments: 0

As AI and high‑performance computing systems continue to scale, memory bandwidth has emerged as a primary system‑level constraint. Larger models, higher compute density, and increasingly complex multi‑die designs are driving the need for memory interfaces that can deliver extreme bandwidth while operating within tight power and signal‑integrity margins. High‑Bandwidth Memory (HBM) has... » read more

Customizing Foundation IP For Ultra-Low-Voltage Designs
By Daryl Seitzer - 12 Mar, 2026 - Comments: 0

By Daryl Seitzer, Andrew Appleby, and Mohammad Tanveer Building a new system-on-chip (SoC) starts with assembling the right foundational elements—pre‑verified IP for logic, memory, I/O, and other essential functions. Standard IP solutions typically address most common design needs, but some projects call for more specialized approaches, especially when innovation is critical or when t... » read more

Power Leadership At 2nm: Foundation IP Optimized For Next-Gen Hyperscale SoCs
By Andrew Appleby - 12 Feb, 2026 - Comments: 0

By Andrew Appleby and Daryl Seitzer As demand for data center compute accelerates, power efficiency has become the defining metric for modern CPUs, GPUs, and AI accelerators. Every watt saved directly impacts the massive operating costs of gigawatt-scale AI data centers, where power and cooling account for 40–60% of operational expenditures. To reduce energy consumption and strengthen t... » read more

The Design Challenges Of Clock Integrity And Clock Jitter
By Manoz Palaparthi - 15 Jan, 2026 - Comments: 0

Signal integrity is one of the many challenges faced by chip designers. Deep submicron technologies are unfriendly hosts for the nice, clean signals desired. The culprits that compromise signal integrity and introduce jitter include thermal effects, manufacturing flaws, signal crosstalk, IR (voltage) drop, signal loss over long runs, reflections, electromagnetic interference (EMI), ground bounc... » read more

PCIe 8.0: Preparing For The Next Doubling
By Monica Olvera - 11 Dec, 2025 - Comments: 0

By Monica Olvera and Gustavo Pimentel Every few years, the industry confronts the same challenge: can general-purpose I/O double again without overwhelming power budgets, overwhelming signal-integrity limits, or fragmenting the ecosystem? With PCIe 8.0, the answer appears to be yes—if the entire stack continues to advance together. Public PCI-SIG information outlines an objective of 256.0 ... » read more

Predictable Design Optimization And Closure With Adaptive Scenario Compression
By James Chuang - 13 Nov, 2025 - Comments: 0

Modern semiconductor chip design faces growing complexity due to numerous timing scenarios driven by varying operating conditions and physical effects. This complexity is especially pronounced in mobile and automotive chips, which require optimization across diverse performance and reliability demands. Designers currently focus on a limited subset of scenarios to manage computational load, but ... » read more

Achieving Reliable 2m+ DAC Connectivity For AI Scale Networks With 224G PHY IP
By Abhinav Kothiala - 16 Oct, 2025 - Comments: 0

As artificial intelligence workloads and hyperscale data centers continue to evolve, the requirements for networking infrastructure are becoming increasingly stringent. High-speed, reliable connectivity is essential to support the massive data flow and low-latency demands of AI-scale environments. Passive direct attach copper (DACs) remains an attractive choice for hyperscalers and system vendo... » read more

System-Level Design For 1.6 Tbps Interoperability In AI Data Centers
By Madhumita Sanyal - 14 Aug, 2025 - Comments: 0

By Madhumita Sanyal and Diwakar Kumaraswamy The rapid escalation of AI/ML workloads—driven by increasingly large language models—is reshaping high-performance computing and AI data center architectures. Real-time inference and large-scale training are pushing the limits of compute and interconnect performance. With model sizes and parameter counts doubling every 4–6 months, infrastruct... » read more

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