Efficient Low Power Verification & Debug Methodology Using Power-Aware Simulation


By Himanshu Bhatt and Shreedhar Ramachandra Isolation, retention, and power switches are some of the important functionalities of power-aware designs that use some of the common low power techniques (e.g.) power shutoff, multi-voltage and advanced techniques (e.g.) DVFS, Low VDD standby, and biasing. The strategies for isolation, retention, and level shifter are specified in the power forma... » read more

Next-Generation Ethernet Interconnects For 400G Hyperscale Data Centers


The need for higher bandwidth with efficient connectivity increases as hyperscale data centers transition to faster, flatter, and more scalable network architectures, such as the 2-tier leaf-spine, as seen in Figure 1. The leaf-spine architecture requires massive interconnects as each leaf switch fans-out to every spine switch, maximizing connectivity between servers. Hardware accelerators, art... » read more

Overcoming Low Power Verification Challenges For Mixed-Signal SoC Designs


With increasing SoC complexity and advanced power-aware architectures, a robust low power verification methodology is important for signing off the design at different stages from RTL through netlist. For mixed-signal SoCs, the challenge is, there is no well-defined low power methodology, nor are the industry’s low power verification tools equipped to handle custom designs. This article propo... » read more

Is Your AI SoC Secure?


As artificial intelligence (AI) enters every application, from IoT to automotive, it is bringing new waves of innovation and business models, along with the need for high-grade security. Hackers try to exploit vulnerabilities at all levels of the system, from the system-on-chip (SoC) up. Therefore, security needs to be integral in the AI process. The protection of AI systems, their data, and th... » read more

Impact Of IP On AI SoCs


The combination of mathematics and processing capability has set in motion a new generation of technology advancements with an entire new world of possibilities related to Artificial Intelligence. AI mimics human behavior using deep learning algorithms. Neural networks are what we define as deep learning, which is a subset of machine learning, which is yet a subset of AI, as shown in Figure 1. ... » read more

Enabling Integrated ADAS Domain Controllers With Automotive IP


Traditionally, the electronic control units (ECUs) for individual Advanced Driver Assistance System (ADAS) applications have been placed throughout the car. The latest automotive architecture will integrate ECUs for multiple ADAS applications into centralized domains to combine multiple ADAS functions. The new class of integrated domain controller ECUs utilize data transferred from the car’s ... » read more

Enabling Ethernet Time-Sensitive Networking With Automotive-Certified IP


Automotive systems are becoming more sophisticated as they combine ADAS applications from emergency braking, collision avoidance, lane departure warning to fully autonomous driving, making predictable latency and guaranteed bandwidth in the automotive network critical. These applications require a high volume of data from different parts of the car for processing and decision making. Due to the... » read more

Developing ASIL Ready SoCs For Self-Driving Cars


Artificial intelligence (AI) and deep learning using neural networks is a powerful technique for enabling advanced driver-assistance systems (ADAS) and greater autonomy in vehicles. As AI research moves rapidly, designers are facing tough competition to provide efficient, flexible, and scalable silicon and software to handle deep learning automotive applications like inferencing in embedded vis... » read more

HDMI 2.1 For A More Immersive Viewing Experience


With the advent of richer television and gaming content, consumers’ expectations have gone from ultra-high-resolution 4K displays to 10K with finer image details, more color gamut, and higher bandwidth. To deliver premium content to digital televisions and trending HDMI-based mobile devices, the HDMI Forum recently announced the HDMI specification, version 2.1. The re-architected HDMI 2.1 off... » read more

32GT/s PCI Express Design Considerations


Today’s networking and rapidly emerging artificial intelligence (AI) applications are requiring more bandwidth in accelerators and GPUs, as well as faster interconnects to transmit and receive greater amounts of data. Towards the middle of 2017 the PCI-SIG industry consortium announced its latest specification, PCIe 5.0, which raised the data rate from 16GT/s to 32GT/s and doubled the link... » read more

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