Shift Left Power-Aware Static Verification


Next-generation SoCs with advanced graphics, computing, machine learning (ML) and artificial intelligence (AI) capabilities are posing new unseen challenges in Low Power Verification. These techniques can introduce critical bugs into a design, especially when the power-management infrastructure interacts with signals that cross clock or reset domains. This can create additional clock-domain cro... » read more

High-Performance DSP And Control Processing For Complex 5G Requirements


In the early 2000s, digital signal processors (DSP) were simple in architecture and limited in performance, but complex in programming. However, they evolved to meet of the increased performance requirements of 3G cellular baseband modem applications. A typical 3G modem system would have a single DSP optimized for dual/quad SIMD MAC performance with basic DSP filter instructions like Fast Fouri... » read more

Is Your Functional Safety An Afterthought?


Imagine the air bag in your car not inflating during a collision or deploying without a crash during driving! These are two of the failure modes associated with the air bag in your car, none of which you as a driver have any control over. The severity of both these failures is of course very high, but which one would you rate as a higher hazard? The probability of getting into an accident is lo... » read more

Accurate Power Analysis Using Real Software Workloads


Over the last decade or so, power consumption has become a major issue in the design of many types of electronic products. Of course, power has always mattered for battery-operated devices, but the complexity of portable electronics and the size of the chips they contain have grown significantly. For plugged-in devices, from desktop computers to server racks in a data center, power plays a majo... » read more

Building Your First Chip For Artificial Intelligence? Read This First


As artificial intelligence (AI) capabilities enter new markets, the IP selected for integration provides the critical components of the AI SoC. But beyond the IP, designers are finding a clear advantage in leveraging AI expertise, services, and tools to ensure the design is delivered on time, with a high level of quality and value to the end customer for new and innovative applications. Over... » read more

The Rising Importance Of Design Planning


Design Planning is often overlooked in the chip design flow. The front-end designer carefully architects the design functionality to produce golden RTL. This is then poured into the synthesis engine to produce logic gates. The synthesized netlist is then thrown over the wall by the front-end designer for physical implementation. The back-end designer receives a gate-level netlist, timing con... » read more

Exascale Emulation Debug Challenges


For years, semiconductor industry surveys have shown that functional verification is the dominant phase in chip development and that debug is the most time-consuming task for verification. The problem is getting worse in today’s era of exascale debug, in which software applications drive tests of more than a billion cycles run in emulation on designs of more than a billion gates. System-on-ch... » read more

The Importance Of Using The Right DDR SDRAM Memory


Selecting the right memory technology is often the most critical decision for achieving the optimal system performance. Designers continue to add more cores and functionality to their SoCs; however, increasing performance while keeping power consumption low and silicon footprint small remains a vital goal. DDR SDRAMs, DRAMs in short, meet these memory requirements by offering a dense, high-perf... » read more

Getting Ready for 32 GT/s PCIe 5.0 Designs


The transition from older PCI Express (PCIe) technologies to the latest Revision 5.0 is on an accelerated path, with system-on-chip (SoC) designers seeing a much faster roll out than they did with PCIe 4.0. The recent release of version 0.9 of the PCIe 5.0 Base Specification locks in the functional changes to the specification, allowing designers to confidently start their designs. With the rap... » read more

Efficient Hierarchical Verification For Low Power Designs


By Susantha Wijesekara and Himanshu Bhatt Growing design sizes, low power (LP) complexity and the need for early stage verification is making designers adopt hierarchical verification flows. Traditionally for hierarchical verification, designers use a black box, liberty model based hierarchical flow, timing model (ETM) flow or stub/glass box flows that offer various degrees of trade-offs for... » read more

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