Special Report
Cloud 2.0
Changes are under development to radically improve efficiency in the data center, with semiconductors and software at the center of this shift.
Top Stories
Moore Memory Problems
The scaling of the 6T SRAM cell is slowing and the surrounding circuitry is getting more complex, so more of the die will be taken up by SRAM at future nodes.
Divide And Conquer: A Power Verification Methodology Approach
While there isn’t a single power verification methodology for every design, there are definitely best practices to follow.
Speeding Up Analog
Part one of three: The difference between analog and digital engineers; integration issues; modeling analog.
Tale Of Two HLS Viewpoints
Was high-level synthesis misguided and has the industry adopted a solution that was ineffective, ill-defined and ill-conceived? The answer depends on your perspective.
Blogs
Editor In Chief Ed Sperling looks at the implications of a breakthrough by IBM, GlobalFoundries and Samsung, in Here Comes 7nm.
Executive Editor Ann Steffora Mutschler questions how to improve verification, in Verification Quality Comes Into Focus.
Mentor’s Robin Bornoff observes that thermal simulation provides more than an indication of operating temperatures—including insights into the physics of heat removal in a particular application as well as better decisions for a product’s thermal design, in How To Get The Most Power While Being Cool To The Touch.
Rambus’ Loren Shalinsky contends that server market growth continues, despite the misleading statistics, in Don’t Let The Headlines Trick You.
Atrenta’s Kiran Vittal finds that static checks are a good supplement to simulation-based verification, in SoC Connectivity Verification Nightmare.
Synopsys’ Ralph Grundler notes that some designers prefer to buy controllers and PHYs separately, but many are now asking for pre-verified interface IP subsystems, in Interface IP Subsystems Speed TTM.
