Top Stories

Optimizing Power For Learning At The Edge
Making learning on the edge work requires a significant reduction in power, which means rethinking all parts of the flow.

Determining Where Power Analysis Matters Most
Need for accuracy varies greatly, depending on where in the design flow it is used and the overall system architecture.

HBM2E: The E Stands For Evolutionary
The new version of the high bandwidth memory standard promises greater speeds and feeds and that’s about it.

Video

In-Memory Computing
Why this approach is so interesting today, and what it really entails.

Blogs

Editor In Chief Ed Sperling finds that more data and new applications are driving demand for performance once again, in Speed Returns As The Key Metric.

Mentor’s Durgesh Prasad, Jitesh Bansal, and Madhur Bhargava explain the differences between RTL UPF and gate-level UPF, and why it is important to create files that require minimal changes when re-used, in Writing Reusable UPF For RTL And Gate-Level Low Power Verification.

Fraunhofer EAS’s Benjamin Prautsch demonstrates why generators for schematics, test benches, simulation control, and layouts can significantly increase efficiency in the various design phases, in Getting To Tape-Out Quicker With Analog Layout Generators.

Synopsys’ Jamileh Davoudi advises that the earlier functional safety analysis is performed in the design cycle, the higher the chance of identifying hotspots and meeting target ASIL, in Is Your Functional Safety An Afterthought?

Adesto’s Apurba Pradhan observes that when disconnected silos of automation can share data, efficiencies can be gained, in Building Automation And Industrial IoT Converge.